From 29a837bd5aeab3da69b3b6cc7c6619b99831b751 Mon Sep 17 00:00:00 2001 From: Julian Intronati Date: Thu, 27 Mar 2025 14:13:50 +0000 Subject: [PATCH] mb/cwwk: Add CWWK CW-ADLNTB-1C2L-V3.0 board as an adl variants This board is the CWWK variant based upon Alder Lake with 2 2.5 GbE ports. The variants files structure is inspired by system76/adl/variants structure, adapted for cw-adl-4l-v1.0 board and the new cw-adlnth-1c2l-v3.0 (named according to original bios naming). CPU: Intel N100 or N305 Memory: 1x DDR5-4800 SODIMM (max 16 GB) NIC: 2x Intel I226-V 2.5 GbE Expansion: - M.2 2230 E key - M.2 2280 M key - USB 2.0 header - Fan header External ports: - DC power - 2x Ethernet - 2x HDMI - 2x USB 2.0 Working: - Boots Debian 12 with SeaBIOS and EDK II payloads - Serial port - External USB ports - 1x HDMI - 2x Intel I226 2.5 GbE NICs - M.2 ports - ACPI S3 - Fan (ITE IT8613E) driver IT87 (frankcrawford github fork) Not tested: - The second HDMI - Audio - S0ix (cw-adl-4l-v1.0 said it's not working) - Internal USB ports VBT extracted from vendor UEFI firmware version F2 (2024-06-26 10:26:38) was 100% matching the cw-adl-4l-v1.0, so we kept only one in the tree. Change-Id: Ia0553141b41717b560042de1136d53b9c3cf7a69 Signed-off-by: Julian Intronati Reviewed-on: https://review.coreboot.org/c/coreboot/+/87027 Reviewed-by: Julian Intronati Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/cwwk/adl/Kconfig | 31 +- src/mainboard/cwwk/adl/Kconfig.name | 5 +- src/mainboard/cwwk/adl/Makefile.mk | 7 +- src/mainboard/cwwk/adl/board_info.txt | 2 +- .../cwwk/adl/include/mainboard/gpio.h | 8 + .../cwwk/adl/{mainboard.c => ramstage.c} | 4 +- .../variants/cw-adl-4l-v1.0/board_info.txt | 2 + .../cw-adl-4l-v1.0/gpio.c} | 9 +- .../cw-adl-4l-v1.0/romstage.c} | 0 .../cw-adlntb-1c2l-v3.0/board_info.txt | 2 + .../adl/variants/cw-adlntb-1c2l-v3.0/gpio.c | 298 ++++++++++++++++++ .../variants/cw-adlntb-1c2l-v3.0/romstage.c | 28 ++ 12 files changed, 382 insertions(+), 14 deletions(-) create mode 100644 src/mainboard/cwwk/adl/include/mainboard/gpio.h rename src/mainboard/cwwk/adl/{mainboard.c => ramstage.c} (71%) create mode 100644 src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/board_info.txt rename src/mainboard/cwwk/adl/{gpio.h => variants/cw-adl-4l-v1.0/gpio.c} (98%) rename src/mainboard/cwwk/adl/{romstage_fsp_params.c => variants/cw-adl-4l-v1.0/romstage.c} (100%) create mode 100644 src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/board_info.txt create mode 100644 src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/gpio.c create mode 100644 src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/romstage.c diff --git a/src/mainboard/cwwk/adl/Kconfig b/src/mainboard/cwwk/adl/Kconfig index c8dbd04dd7..11b8e3c9c4 100644 --- a/src/mainboard/cwwk/adl/Kconfig +++ b/src/mainboard/cwwk/adl/Kconfig @@ -1,8 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -if BOARD_CWWK_ADL_N - -config BOARD_SPECIFIC_OPTIONS +config BOARD_CWWK_ADL_N_COMMON def_bool y select BOARD_ROMSIZE_KB_16384 select CRB_TPM @@ -15,11 +13,36 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_ALDERLAKE_PCH_N select SUPERIO_ITE_IT8613E +config BOARD_CWWK_CW_ADL_4L_V1 + select BOARD_CWWK_ADL_N_COMMON + +config BOARD_CWWK_CW_ADLNTB_1C2L_V3 + select BOARD_CWWK_ADL_N_COMMON + +if BOARD_CWWK_ADL_N_COMMON + config MAINBOARD_DIR default "cwwk/adl" +config VARIANT_DIR + default "cw-adl-4l-v1.0" if BOARD_CWWK_CW_ADL_4L_V1 + default "cw-adlntb-1c2l-v3.0" if BOARD_CWWK_CW_ADLNTB_1C2L_V3 + config MAINBOARD_PART_NUMBER - default "CW-AL-4L-V1.0" + default "CW-ADL-4L-V1.0" if BOARD_CWWK_CW_ADL_4L_V1 + default "CW-ADLNTB-1C2L-V3.0" if BOARD_CWWK_CW_ADLNTB_1C2L_V3 + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "CW-ADL-4L-V1.0" if BOARD_CWWK_CW_ADL_4L_V1 + default "CW-X86-P5-V3" if BOARD_CWWK_CW_ADLNTB_1C2L_V3 + +config MAINBOARD_VERSION + default "CW-ADL-4L-V1.0" if BOARD_CWWK_CW_ADL_4L_V1 + default "CW-ADLNTB-1C2L-V3.0" if BOARD_CWWK_CW_ADLNTB_1C2L_V3 + +# Override the default variant behavior, since the data.vbt is the same +config INTEL_GMA_VBT_FILE + default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" config NO_POST default y diff --git a/src/mainboard/cwwk/adl/Kconfig.name b/src/mainboard/cwwk/adl/Kconfig.name index 7faa8e4831..d102e3249f 100644 --- a/src/mainboard/cwwk/adl/Kconfig.name +++ b/src/mainboard/cwwk/adl/Kconfig.name @@ -1,4 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -config BOARD_CWWK_ADL_N +config BOARD_CWWK_CW_ADL_4L_V1 bool "CW-ADL-4L-V1.0" + +config BOARD_CWWK_CW_ADLNTB_1C2L_V3 + bool "CW-ADLNTB-1C2L-V3.0" diff --git a/src/mainboard/cwwk/adl/Makefile.mk b/src/mainboard/cwwk/adl/Makefile.mk index 89eb072db2..432208bf6c 100644 --- a/src/mainboard/cwwk/adl/Makefile.mk +++ b/src/mainboard/cwwk/adl/Makefile.mk @@ -1,7 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + bootblock-y += bootblock.c -romstage-y += romstage_fsp_params.c +romstage-y += variants/$(VARIANT_DIR)/romstage.c -ramstage-y += mainboard.c +ramstage-y += ramstage.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/mainboard/cwwk/adl/board_info.txt b/src/mainboard/cwwk/adl/board_info.txt index b53863c87c..7166620e9b 100644 --- a/src/mainboard/cwwk/adl/board_info.txt +++ b/src/mainboard/cwwk/adl/board_info.txt @@ -1,6 +1,6 @@ Vendor name: CWWK -Board name: CW-ADL-4L-V1.0 Category: eval +ROM package: SOIC-8 ROM protocol: SPI ROM socketed: n Flashrom support: y diff --git a/src/mainboard/cwwk/adl/include/mainboard/gpio.h b/src/mainboard/cwwk/adl/include/mainboard/gpio.h new file mode 100644 index 0000000000..ef2a21c418 --- /dev/null +++ b/src/mainboard/cwwk/adl/include/mainboard/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/cwwk/adl/mainboard.c b/src/mainboard/cwwk/adl/ramstage.c similarity index 71% rename from src/mainboard/cwwk/adl/mainboard.c rename to src/mainboard/cwwk/adl/ramstage.c index b15d01728b..fb968e1026 100644 --- a/src/mainboard/cwwk/adl/mainboard.c +++ b/src/mainboard/cwwk/adl/ramstage.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include #include -#include "gpio.h" static void mainboard_init(void *chip_info) { - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + mainboard_configure_gpios(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/board_info.txt b/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/board_info.txt new file mode 100644 index 0000000000..5eba41ce2b --- /dev/null +++ b/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/board_info.txt @@ -0,0 +1,2 @@ +Board name: CW-ADL-4L-V1.0 +Release year: 2024 diff --git a/src/mainboard/cwwk/adl/gpio.h b/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/gpio.c similarity index 98% rename from src/mainboard/cwwk/adl/gpio.h rename to src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/gpio.c index fc3d7ead15..0223539cbb 100644 --- a/src/mainboard/cwwk/adl/gpio.h +++ b/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/gpio.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef CFG_GPIO_H -#define CFG_GPIO_H - +#include #include /* Pad configuration was generated automatically using intelp2m utility */ @@ -294,4 +292,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_R7, NONE), /* GPIO */ }; -#endif /* CFG_GPIO_H */ +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/cwwk/adl/romstage_fsp_params.c b/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/romstage.c similarity index 100% rename from src/mainboard/cwwk/adl/romstage_fsp_params.c rename to src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/romstage.c diff --git a/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/board_info.txt b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/board_info.txt new file mode 100644 index 0000000000..e466a7a513 --- /dev/null +++ b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/board_info.txt @@ -0,0 +1,2 @@ +Board name: CW-X86-P5-V3 +Release year: 2024 diff --git a/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/gpio.c b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/gpio.c new file mode 100644 index 0000000000..ab16207ea0 --- /dev/null +++ b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/gpio.c @@ -0,0 +1,298 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), /* VRALERT# */ + PAD_NC(GPP_B3, NONE), /* GPIO */ + PAD_NC(GPP_B4, NONE), /* GPIO */ + PAD_NC(GPP_B5, NONE), /* GPIO */ + PAD_NC(GPP_B6, NONE), /* GPIO */ + PAD_NC(GPP_B7, NONE), /* GPIO */ + PAD_NC(GPP_B8, NONE), /* GPIO */ + PAD_NC(GPP_B9, NONE), /* GPIO */ + PAD_NC(GPP_B10, NONE), /* GPIO */ + //PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), /* PMCALERT# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# */ + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), /* SPKR */ + PAD_NC(GPP_B15, NONE), /* GPIO */ + PAD_NC(GPP_B16, NONE), /* GPIO */ + PAD_NC(GPP_B17, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), /* GPIO */ + PAD_NC(GPP_B19, NONE), /* GPIO */ + PAD_NC(GPP_B20, NONE), /* GPIO */ + PAD_NC(GPP_B21, NONE), /* GPIO */ + PAD_NC(GPP_B22, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1), /* GSPI0_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1), /* GSPI1_CLK_LOOPBK */ + + /* ------- GPIO Group GPP_T ------- */ + PAD_NC(GPP_T0, NONE), /* GPIO */ + PAD_NC(GPP_T1, NONE), /* GPIO */ + PAD_CFG_NF(GPP_T2, DN_20K, DEEP, NF2), /* FUSA_DIAGTEST_EN */ + PAD_CFG_NF(GPP_T3, DN_20K, DEEP, NF2), /* FUSA_DIAGTEST_MODE */ + PAD_NC(GPP_T4, NONE), /* GPIO */ + PAD_NC(GPP_T5, NONE), /* GPIO */ + PAD_NC(GPP_T6, NONE), /* GPIO */ + PAD_NC(GPP_T7, NONE), /* GPIO */ + PAD_NC(GPP_T8, NONE), /* GPIO */ + PAD_NC(GPP_T9, NONE), /* GPIO */ + PAD_NC(GPP_T10, NONE), /* GPIO */ + PAD_NC(GPP_T11, NONE), /* GPIO */ + PAD_NC(GPP_T12, NONE), /* GPIO */ + PAD_NC(GPP_T13, NONE), /* GPIO */ + PAD_NC(GPP_T14, NONE), /* GPIO */ + PAD_NC(GPP_T15, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), /* ESPI_IO0 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), /* ESPI_IO1 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), /* ESPI_IO2 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), /* ESPI_IO3 */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* ESPI_CS0# */ + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), /* ESPI_ALERT0# */ + PAD_CFG_NF(GPP_A6, UP_20K, DEEP, NF1), /* ESPI_ALERT1# */ + PAD_CFG_GPO(GPP_A7, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_A8, 0, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* ESPI_CLK */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* ESPI_RESET# */ + PAD_CFG_GPO(GPP_A11, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_A12, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), /* GPIO */ + PAD_NC(GPP_A14, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_A15, 1, DEEP), /* GPIO */ + PAD_NC(GPP_A16, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_A17, 1, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* DDSP_HPDB */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* DDSP_HPD1 */ + PAD_NC(GPP_A20, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_A21, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_A22, NONE), /* GPIO */ + PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1), /* ESPI_CS1# */ + PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1), /* GPP_ESPI_CLK_LOOPBK */ + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), /* GPIO */ + PAD_NC(GPP_S1, NONE), /* GPIO */ + PAD_NC(GPP_S2, NONE), /* GPIO */ + PAD_NC(GPP_S3, NONE), /* GPIO */ + PAD_NC(GPP_S4, NONE), /* GPIO */ + PAD_NC(GPP_S5, NONE), /* GPIO */ + PAD_NC(GPP_S6, NONE), /* GPIO */ + PAD_NC(GPP_S7, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_I ------- */ + PAD_NC(GPP_I0, NONE), /* GPIO */ + PAD_NC(GPP_I1, NONE), /* GPIO */ + PAD_NC(GPP_I2, NONE), /* GPIO */ + PAD_NC(GPP_I3, NONE), /* GPIO */ + PAD_NC(GPP_I4, NONE), /* GPIO */ + PAD_NC(GPP_I5, NONE), /* GPIO */ + PAD_NC(GPP_I6, NONE), /* GPIO */ + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), /* EMMC_CMD */ + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), /* EMMC_DATA0 */ + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), /* EMMC_DATA1 */ + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), /* EMMC_DATA2 */ + PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), /* EMMC_DATA3 */ + PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), /* EMMC_DATA4 */ + PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), /* EMMC_DATA5 */ + PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), /* EMMC_DATA6 */ + PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), /* EMMC_DATA7 */ + PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), /* EMMC_RCLK */ + PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), /* EMMC_CLK */ + PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), /* EMMC_RESET# */ + PAD_NC(GPP_I19, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H1, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H2, 1, RSMRST), /* GPIO */ + PAD_CFG_GPO(GPP_H3, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_H4, NONE), /* GPIO */ + PAD_NC(GPP_H5, NONE), /* GPIO */ + PAD_NC(GPP_H6, NONE), /* GPIO */ + PAD_NC(GPP_H7, NONE), /* GPIO */ + PAD_NC(GPP_H8, NONE), /* GPIO */ + PAD_NC(GPP_H9, NONE), /* GPIO */ + PAD_NC(GPP_H10, NONE), /* GPIO */ + PAD_NC(GPP_H11, NONE), /* GPIO */ + PAD_NC(GPP_H12, NONE), /* GPIO */ + PAD_NC(GPP_H13, NONE), /* GPIO */ + PAD_NC(GPP_H14, NONE), /* GPIO */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ + PAD_NC(GPP_H16, NONE), /* GPIO */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* PROC_C10_GATE# */ + PAD_NC(GPP_H19, NONE), /* GPIO */ + PAD_NC(GPP_H20, NONE), /* GPIO */ + PAD_NC(GPP_H21, NONE), /* GPIO */ + PAD_NC(GPP_H22, NONE), /* GPIO */ + PAD_NC(GPP_H23, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), /* GPIO */ + PAD_NC(GPP_D1, NONE), /* GPIO */ + PAD_NC(GPP_D2, NONE), /* GPIO */ + PAD_NC(GPP_D3, NONE), /* GPIO */ + PAD_NC(GPP_D4, NONE), /* GPIO */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* SRCCLKREQ0# */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* SRCCLKREQ1# */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* SRCCLKREQ2# */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* SRCCLKREQ3# */ + PAD_CFG_NF(GPP_D9, NATIVE, DEEP, NF5), /* BSSB_LS2_RX */ + PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF5), /* BSSB_LS2_TX */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF5), /* BSSB_LS3_TX */ + PAD_CFG_GPO(GPP_D13, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D14, 1, DEEP), /* GPIO */ + PAD_NC(GPP_D15, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_D17, NONE), /* GPIO */ + PAD_NC(GPP_D18, NONE), /* GPIO */ + PAD_NC(GPP_D19, NONE), /* GPIO */ + PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1), /* GPP_GSPI2_CLK_LOOPBK */ + + /* ------- GPIO Group vGPIO ------- */ + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPP_GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), /* BATLOW# */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* ACPRESENT */ + PAD_CFG_GPO(GPD2, 1, DEEP), /* GPIO */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* PWRBTN# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S3# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_S4# */ + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* SLP_A# */ + PAD_CFG_GPO(GPD7, 1, PLTRST), /* GPIO */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK */ + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_WLAN# */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* SLP_S5# */ + PAD_CFG_GPO(GPD11, 0, PWROK), /* GPIO */ + PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1), /* GPD_INPUT3VSEL */ + PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1), /* GPD_SLP_LANB */ + PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1), /* GPD_SLP_SUSB */ + PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1), /* GPD_WAKEB */ + PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1), /* GPD_DRAM_RESETB */ + + /* ------- GPIO Group PCIe vGPIO ------- */ + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */ + PAD_CFG_GPO(GPP_C2, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0CLK */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0DATA */ + PAD_CFG_GPO(GPP_C5, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1), /* SML1CLK */ + PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1), /* SML1DATA */ + PAD_NC(GPP_C8, NONE), /* GPIO */ + PAD_NC(GPP_C9, NONE), /* GPIO */ + PAD_NC(GPP_C10, NONE), /* GPIO */ + PAD_NC(GPP_C11, NONE), /* GPIO */ + PAD_NC(GPP_C12, NONE), /* GPIO */ + PAD_NC(GPP_C13, NONE), /* GPIO */ + PAD_NC(GPP_C14, NONE), /* GPIO */ + PAD_NC(GPP_C15, NONE), /* GPIO */ + PAD_NC(GPP_C16, NONE), /* GPIO */ + PAD_NC(GPP_C17, NONE), /* GPIO */ + PAD_NC(GPP_C18, NONE), /* GPIO */ + PAD_NC(GPP_C19, NONE), /* GPIO */ + PAD_NC(GPP_C20, NONE), /* GPIO */ + PAD_NC(GPP_C21, NONE), /* GPIO */ + PAD_NC(GPP_C22, NONE), /* GPIO */ + PAD_NC(GPP_C23, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_BRI_DT */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* CNV_RGI_DT */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_RF_RESET# */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), /* MODEM_CLKREQ */ + PAD_NC(GPP_F6, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_F7, 0, DEEP), /* GPIO */ + PAD_NC(GPP_F8, NONE), /* GPIO */ + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* BOOTMPC */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_F11, NONE), /* GPIO */ + PAD_NC(GPP_F12, NONE), /* GPIO */ + PAD_NC(GPP_F13, NONE), /* GPIO */ + PAD_NC(GPP_F14, NONE), /* GPIO */ + PAD_NC(GPP_F15, NONE), /* GPIO */ + PAD_NC(GPP_F16, NONE), /* GPIO */ + PAD_NC(GPP_F17, NONE), /* GPIO */ + PAD_NC(GPP_F18, NONE), /* GPIO */ + PAD_NC(GPP_F19, NONE), /* GPIO */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* Reserved */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* Reserved */ + PAD_NC(GPP_F22, NONE), /* GPIO */ + PAD_NC(GPP_F23, NONE), /* GPIO */ + PAD_NC(GPP_F_CLK_LOOPBK, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_HVCMOS ------- */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1), /* n/a */ + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), /* GPIO */ + PAD_NC(GPP_E1, NONE), /* GPIO */ + PAD_NC(GPP_E2, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E4, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_E5, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_E6, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_E8, NONE), /* GPIO */ + PAD_NC(GPP_E9, NONE), /* GPIO */ + PAD_NC(GPP_E10, NONE), /* GPIO */ + PAD_NC(GPP_E11, NONE), /* GPIO */ + PAD_NC(GPP_E12, NONE), /* GPIO */ + PAD_NC(GPP_E13, NONE), /* GPIO */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDSP_HPDA */ + PAD_CFG_GPO(GPP_E15, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_E16, 0, PLTRST), /* GPIO */ + PAD_NC(GPP_E17, NONE), /* GPIO */ + PAD_NC(GPP_E18, NATIVE), /* GPIO */ + PAD_NC(GPP_E19, NATIVE), /* GPIO */ + PAD_NC(GPP_E20, NONE), /* GPIO */ + PAD_NC(GPP_E21, NONE), /* GPIO */ + PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1), /* DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), /* DDPA_CTRLDATA */ + PAD_NC(GPP_E_CLK_LOOPBK, NONE), /* GPIO */ + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), /* HDA_BCLK */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), /* HDA_SYNC */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), /* HDA_SDO */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), /* HDA_SDI0 */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), /* HDA_RST# */ + PAD_NC(GPP_R5, NONE), /* GPIO */ + PAD_NC(GPP_R6, NONE), /* GPIO */ + PAD_NC(GPP_R7, NONE), /* GPIO */ +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/romstage.c b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/romstage.c new file mode 100644 index 0000000000..cd32138416 --- /dev/null +++ b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/romstage.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + static const struct mb_cfg ddr5_mem_config = { + .type = MEM_TYPE_DDR5, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, + + .LpDdrDqDqsReTraining = 1, + }; + + const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x52, }, + }, + }; + + const bool half_populated = false; + memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, half_populated); +}