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UPSTREAM: AGESA: Fix invalid use of CFG_ declarations

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The declarations of CFG_ evaluate to correct values only when
included after the definitions of BLDCFG_ in buildOpts.c.
So we never have CFG_PLAT_NUM_IO_APICS defined here.

Change-Id: I94b3dee5a3207b37921eb24a0bcd73b5a217b2d3
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/14887
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 5003632407)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/350081
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-05-18 13:35:21 +03:00 • committed by chrome-bot
commit 28b1736f61
4 changed files with 20 additions and 20 deletions
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10
src/northbridge/amd/agesa/family15/northbridge.c
View file

@ -1081,11 +1081,11 @@ static void cpu_bus_scan(device_t dev)
* This is needed because many IO-APIC devices only have 4 bits
* for their APIC id and therefore must reside at 0..15
*/
#ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */
#define CFG_PLAT_NUM_IO_APICS 3
#endif
if ((node_nums * core_max) + CFG_PLAT_NUM_IO_APICS >= 0x10) {
lapicid_start = (CFG_PLAT_NUM_IO_APICS - 1) / core_max;
u8 plat_num_io_apics = 3; /* FIXME */
if ((node_nums * core_max) + plat_num_io_apics >= 0x10) {
lapicid_start = (plat_num_io_apics - 1) / core_max;
lapicid_start = (lapicid_start + 1) * core_max;
printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
}

10
src/northbridge/amd/agesa/family15rl/northbridge.c
View file

@ -1071,11 +1071,11 @@ static void cpu_bus_scan(device_t dev)
* This is needed because many IO-APIC devices only have 4 bits
* for their APIC id and therefore must reside at 0..15
*/
#ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */
#define CFG_PLAT_NUM_IO_APICS 3
#endif
if ((node_nums * core_max) + CFG_PLAT_NUM_IO_APICS >= 0x10) {
lapicid_start = (CFG_PLAT_NUM_IO_APICS - 1) / core_max;
u8 plat_num_io_apics = 3; /* FIXME */
if ((node_nums * core_max) + plat_num_io_apics >= 0x10) {
lapicid_start = (plat_num_io_apics - 1) / core_max;
lapicid_start = (lapicid_start + 1) * core_max;
printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
}

10
src/northbridge/amd/agesa/family15tn/northbridge.c
View file

@ -1070,11 +1070,11 @@ static void cpu_bus_scan(device_t dev)
* This is needed because many IO-APIC devices only have 4 bits
* for their APIC id and therefore must reside at 0..15
*/
#ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */
#define CFG_PLAT_NUM_IO_APICS 3
#endif
if ((node_nums * core_max) + CFG_PLAT_NUM_IO_APICS >= 0x10) {
lapicid_start = (CFG_PLAT_NUM_IO_APICS - 1) / core_max;
u8 plat_num_io_apics = 3; /* FIXME */
if ((node_nums * core_max) + plat_num_io_apics >= 0x10) {
lapicid_start = (plat_num_io_apics - 1) / core_max;
lapicid_start = (lapicid_start + 1) * core_max;
printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
}

10
src/northbridge/amd/agesa/family16kb/northbridge.c
View file

@ -1087,11 +1087,11 @@ static void cpu_bus_scan(device_t dev)
* This is needed because many IO-APIC devices only have 4 bits
* for their APIC id and therefore must reside at 0..15
*/
#ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */
#define CFG_PLAT_NUM_IO_APICS 3
#endif
if ((node_nums * core_max) + CFG_PLAT_NUM_IO_APICS >= 0x10) {
lapicid_start = (CFG_PLAT_NUM_IO_APICS - 1) / core_max;
u8 plat_num_io_apics = 3; /* FIXME */
if ((node_nums * core_max) + plat_num_io_apics >= 0x10) {
lapicid_start = (plat_num_io_apics - 1) / core_max;
lapicid_start = (lapicid_start + 1) * core_max;
printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
}