From 289c01e6fb3c56919fc4782a32660d154b7ab45d Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Mon, 15 Sep 2025 11:04:12 -0700 Subject: [PATCH] mb/google/ocelot: implement variant_memory_sku() Ocelot uses the CHROMEOS_DRAM_PART_NUMBER_IN_CBI Kconfig option because the hardware does not have DRAM ID straps, but this option was designed for boards that would only ever have a single memory option. In order to support multiple memory parts, we need to create a table that maps memory part number to DRAM id so that we can select the correct SPD for the memory, and then override the variant_memory_sku() routine so that we can determine and return the correct DRAM id for the memory part number specified in the CBI. BUG=b:443646405 TEST=Change DRAM part number in CBI to "H58G66BK7BX067", reboot ocelot and verify the AP boot logs show that the SPD index = 1. Change-Id: I18ba6c4891c6053f40e99dcde8a06b9efc1d95f4 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/89183 Tested-by: build bot (Jenkins) Reviewed-by: Appukuttan V K Reviewed-by: Karthik Ramasubramanian --- .../google/ocelot/variants/ocelot/Makefile.mk | 1 + .../google/ocelot/variants/ocelot/memory.c | 2 +- .../variants/ocelot/part_num_to_dram_id.c | 35 +++++++++++++++++++ 3 files changed, 37 insertions(+), 1 deletion(-) create mode 100644 src/mainboard/google/ocelot/variants/ocelot/part_num_to_dram_id.c diff --git a/src/mainboard/google/ocelot/variants/ocelot/Makefile.mk b/src/mainboard/google/ocelot/variants/ocelot/Makefile.mk index 3fdd4642c0..1ec5666ec1 100644 --- a/src/mainboard/google/ocelot/variants/ocelot/Makefile.mk +++ b/src/mainboard/google/ocelot/variants/ocelot/Makefile.mk @@ -4,6 +4,7 @@ bootblock-y += gpio.c romstage-y += gpio.c romstage-y += memory.c romstage-$(CONFIG_FW_CONFIG) += fw_config.c +romstage-$(CONFIG_CHROMEOS_DRAM_PART_NUMBER_IN_CBI) += part_num_to_dram_id.c ramstage-y += gpio.c romstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/ocelot/variants/ocelot/memory.c b/src/mainboard/google/ocelot/variants/ocelot/memory.c index 7ac5ce95fd..43f40a9629 100644 --- a/src/mainboard/google/ocelot/variants/ocelot/memory.c +++ b/src/mainboard/google/ocelot/variants/ocelot/memory.c @@ -82,7 +82,7 @@ const struct mb_cfg *variant_memory_params(void) void variant_get_spd_info(struct mem_spd *spd_info) { uint32_t id = board_id() & BOARD_ID_MASK; - spd_info->cbfs_index = 0; + spd_info->cbfs_index = variant_memory_sku(); switch (id) { case BOARD_ID_DDR5: diff --git a/src/mainboard/google/ocelot/variants/ocelot/part_num_to_dram_id.c b/src/mainboard/google/ocelot/variants/ocelot/part_num_to_dram_id.c new file mode 100644 index 0000000000..c73e5c9a12 --- /dev/null +++ b/src/mainboard/google/ocelot/variants/ocelot/part_num_to_dram_id.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +struct part_num_spd_index { + const char part_num[DIMM_INFO_PART_NUMBER_SIZE]; + int spd_index; +}; + +static const struct part_num_spd_index part_number_map[] = { + { "H58G56BK8BX068", 0 }, + { "H58G66BK7BX067", 1 }, + { "H58G66BK8BX067", 2 }, + { "H58GE6AK8BX104", 3 }, + { "H58G66CK8BX147", 2 }, +}; + +int variant_memory_sku(void) +{ + int index; + size_t num_elements = ARRAY_SIZE(part_number_map); + const char *part_num = mainboard_get_dram_part_num(); + + if (part_num == NULL) + die("No part number in CBI, halting boot.\n"); + + for (index = 0; index < num_elements; index++) { + if (!strcmp(part_num, part_number_map[index].part_num)) + /* exact match found */ + return part_number_map[index].spd_index; + } + + /* We didn't find a match for part_num, halt boot */ + die("No part number found looking for %s, halting boot.\n", part_num); +}