From 28930e9c18cefb19aa1996bbfd3fad3538b6bb1f Mon Sep 17 00:00:00 2001 From: Pranava Y N Date: Fri, 28 Feb 2025 17:14:48 +0530 Subject: [PATCH] mb/google/brya/nova: Enable RTD3 for SSD to resolve S0ix issue Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Enable and reset GPIOs are configured as per pin mapping in gpio.c. BUG=b:391612392 TEST=Run suspend_stress_test on nova and verify that the device suspends to S0ix. Change-Id: Icb36285d0a12dcb098282b08ef794256af67b019 Signed-off-by: Pranava Y N Reviewed-on: https://review.coreboot.org/c/coreboot/+/86649 Reviewed-by: Subrata Banik Reviewed-by: Eric Lai Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) --- src/mainboard/google/brya/variants/nova/overridetree.cb | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/google/brya/variants/nova/overridetree.cb b/src/mainboard/google/brya/variants/nova/overridetree.cb index c8bfc31b08..a615fdd70b 100644 --- a/src/mainboard/google/brya/variants/nova/overridetree.cb +++ b/src/mainboard/google/brya/variants/nova/overridetree.cb @@ -185,6 +185,13 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end end device ref cnvi_wifi on chip drivers/wifi/generic