From 28608c503a0405a0e659d26e826f1bddb40c7a0d Mon Sep 17 00:00:00 2001 From: Pranava Y N Date: Tue, 3 Feb 2026 18:28:10 +0530 Subject: [PATCH] Revert "soc/intel/pantherlake: Enable all RootPorts on PTL-H484" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 261274992d03a41c75819c1e7b24bdbb5e4eba7a. Reason for revert: Panther Lake U/H Processor EDS vol 1/2 says PTL-U/H 12Xe has 12 PCIe RPs where else PTL-H 4Xe has 10 PCIe RPs. This change has limit the capability for devices that is build with PTL-U/H 12Xe hence, we are seeing below errors ``` [ERROR] pcie_rp_update_devicetree: Error: Group exceeds CONFIG_MAX_ROOT_PORTS. ``` As a result PCIe Gen 5 devices (SSD) unable to init and enabled during boot. Change-Id: I0443554ef8f619c485f16edc576794f9cf2e85ea Signed-off-by: Pranava Y N Reviewed-on: https://review.coreboot.org/c/coreboot/+/91075 Reviewed-by: Subrata Banik Reviewed-by: Jérémy Compostella Tested-by: build bot (Jenkins) --- src/soc/intel/pantherlake/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 45a8c8376e..59369a6a46 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -253,8 +253,8 @@ config MAX_TBT_ROOT_PORTS config MAX_ROOT_PORTS int default 6 if SOC_INTEL_WILDCATLAKE - default 12 if SOC_INTEL_PANTHERLAKE_H - default 10 + default 10 if SOC_INTEL_PANTHERLAKE_H + default 12 config MAX_PCIE_CLOCK_SRC int