diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index ff291570d2..4b21326648 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -19,6 +19,7 @@ */ #include +#include #include #include #include @@ -30,72 +31,41 @@ #include #include #include -#include #include +#include #include -#include "nvs.h" -#include "pch.h" - -#define NMI_OFF 0 - -#define ENABLE_ACPI_MODE_IN_COREBOOT 0 - -typedef struct southbridge_intel_lynxpoint_config config_t; - -static void pch_enable_apic(struct device *dev) +#include +#include +#include +#include +#include +#include +#include +#include #include +#include +#include + +static void pch_enable_ioapic(struct device *dev) { - int i; u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - pci_write_config8(dev, ACPI_CNTL, 0x80); - - *ioapic_index = 0; - *ioapic_data = (1 << 25); + set_ioapic_id(IO_APIC_ADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - if (pch_is_lp()) { - /* PCH-LP has 39 redirection entries */ - reg32 &= ~0x00ff0000; - reg32 |= 0x00270000; - } - *ioapic_index = 1; - *ioapic_data = reg32; + reg32 = io_apic_read(IO_APIC_ADDR, 0x01); - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die("APIC Error\n"); + /* PCH-LP has 39 redirection entries */ + reg32 &= ~0x00ff0000; + reg32 |= 0x00270000; - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } + io_apic_write(IO_APIC_ADDR, 0x01, reg32); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ -} - -static void pch_enable_serial_irqs(struct device *dev) -{ - /* Set packet length and toggle silent mode bit for one frame. */ - pci_write_config8(dev, SERIRQ_CNTL, - (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); -#if !CONFIG_SERIRQ_CONTINUOUS_MODE - pci_write_config8(dev, SERIRQ_CNTL, - (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); -#endif + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write(IO_APIC_ADDR, 0x03, 0x01); } /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control @@ -122,7 +92,6 @@ static void pch_enable_serial_irqs(struct device *dev) static void pch_pirq_init(device_t dev) { device_t irq_dev; - /* Get the chip configuration */ config_t *config = dev->chip_info; pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); @@ -135,10 +104,6 @@ static void pch_pirq_init(device_t dev) pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); - /* Eric Biederman once said we should let the OS do this. - * I am not so sure anymore he was right. - */ - for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin=0, int_line=0; @@ -161,46 +126,13 @@ static void pch_pirq_init(device_t dev) } } -static void pch_gpi_routing(device_t dev) -{ - /* Get the chip configuration */ - config_t *config = dev->chip_info; - u32 reg32 = 0; - - /* An array would be much nicer here, or some - * other method of doing this. - */ - reg32 |= (config->gpi0_routing & 0x03) << 0; - reg32 |= (config->gpi1_routing & 0x03) << 2; - reg32 |= (config->gpi2_routing & 0x03) << 4; - reg32 |= (config->gpi3_routing & 0x03) << 6; - reg32 |= (config->gpi4_routing & 0x03) << 8; - reg32 |= (config->gpi5_routing & 0x03) << 10; - reg32 |= (config->gpi6_routing & 0x03) << 12; - reg32 |= (config->gpi7_routing & 0x03) << 14; - reg32 |= (config->gpi8_routing & 0x03) << 16; - reg32 |= (config->gpi9_routing & 0x03) << 18; - reg32 |= (config->gpi10_routing & 0x03) << 20; - reg32 |= (config->gpi11_routing & 0x03) << 22; - reg32 |= (config->gpi12_routing & 0x03) << 24; - reg32 |= (config->gpi13_routing & 0x03) << 26; - reg32 |= (config->gpi14_routing & 0x03) << 28; - reg32 |= (config->gpi15_routing & 0x03) << 30; - - pci_write_config32(dev, 0xb8, reg32); -} - static void pch_power_options(device_t dev) { - u8 reg8; u16 reg16; - u32 reg32; const char *state; /* Get the chip configuration */ config_t *config = dev->chip_info; - u16 pmbase = get_pmbase(); int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - int nmi_option; /* Which state do we want to goto after g3 (power restored)? * 0 == S0 Full On @@ -209,7 +141,6 @@ static void pch_power_options(device_t dev) * If the option is not existent (Laptops), use Kconfig setting. */ get_option(&pwr_on, "power_on_after_fail"); - pwr_on = MAINBOARD_POWER_KEEP; reg16 = pci_read_config16(dev, GEN_PMCON_3); reg16 &= 0xfffe; @@ -229,72 +160,15 @@ static void pch_power_options(device_t dev) default: state = "undefined"; } - - reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ - reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ - - reg16 &= ~(1 << 10); - reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ - - reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ - pci_write_config16(dev, GEN_PMCON_3, reg16); printk(BIOS_INFO, "Set power %s after power failure.\n", state); - /* Set up NMI on errors. */ - reg8 = inb(0x61); - reg8 &= 0x0f; /* Higher Nibble must be 0 */ - reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ - // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ - reg8 |= (1 << 2); /* PCI SERR# Disable for now */ - outb(reg8, 0x61); - - reg8 = inb(0x70); - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - printk(BIOS_INFO, "NMI sources enabled.\n"); - reg8 &= ~(1 << 7); /* Set NMI. */ - } else { - printk(BIOS_INFO, "NMI sources disabled.\n"); - reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ - } - outb(reg8, 0x70); - - /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ - reg16 = pci_read_config16(dev, GEN_PMCON_1); - reg16 &= ~(3 << 0); // SMI# rate 1 minute - reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME - pci_write_config16(dev, GEN_PMCON_1, reg16); - - /* - * Set the board's GPI routing on LynxPoint-H. - * This is done as part of GPIO configuration on LynxPoint-LP. - */ - if (pch_is_lp()) - pch_gpi_routing(dev); - /* GPE setup based on device tree configuration */ enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, config->gpe0_en_3, config->gpe0_en_4); /* SMI setup based on device tree configuration */ enable_alt_smi(config->alt_gp_smi_en); - - /* Set up power management block and determine sleep mode */ - reg32 = inl(pmbase + 0x04); // PM1_CNT - reg32 &= ~(7 << 10); // SLP_TYP - reg32 |= (1 << 0); // SCI_EN - outl(reg32, pmbase + 0x04); - - /* Clear magic status bits to prevent unexpected wake */ - reg32 = RCBA32(0x3310); - reg32 |= (1 << 4)|(1 << 5)|(1 << 0); - RCBA32(0x3310) = reg32; - - reg32 = RCBA32(0x3f02); - reg32 &= ~0xf; - RCBA32(0x3f02) = reg32; } static void pch_rtc_init(struct device *dev) @@ -307,169 +181,167 @@ static void pch_rtc_init(struct device *dev) if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(dev, GEN_PMCON_3, reg8); -#if CONFIG_ELOG - elog_add_event(ELOG_TYPE_RTC_RESET); -#endif + printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); } - printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); - rtc_init(rtc_failed); + cmos_init(rtc_failed); } -/* LynxPoint PCH Power Management init */ -static void lpt_pm_init(struct device *dev) -{ - printk(BIOS_DEBUG, "LynxPoint PM init\n"); -} - -const struct rcba_config_instruction lpt_lp_pm_rcba[] = { - RCBA_RMW_REG_32(0x232c, ~1, 0x00000000), - RCBA_RMW_REG_32(0x1100, ~0xc000, 0xc000), - RCBA_RMW_REG_32(0x1100, ~0, 0x00000100), - RCBA_RMW_REG_32(0x1100, ~0, 0x0000003f), - RCBA_RMW_REG_32(0x2320, ~0x60, 0x10), - RCBA_RMW_REG_32(0x3314, 0, 0x00012fff), - RCBA_RMW_REG_32(0x3318, 0, 0x0dcf0400), - RCBA_RMW_REG_32(0x3324, 0, 0x04000000), - RCBA_RMW_REG_32(0x3368, 0, 0x00041400), - RCBA_RMW_REG_32(0x3388, 0, 0x3f8ddbff), - RCBA_RMW_REG_32(0x33ac, 0, 0x00007001), - RCBA_RMW_REG_32(0x33b0, 0, 0x00181900), - RCBA_RMW_REG_32(0x33c0, 0, 0x00060A00), - RCBA_RMW_REG_32(0x33d0, 0, 0x06200840), - RCBA_RMW_REG_32(0x3a28, 0, 0x01010101), - RCBA_RMW_REG_32(0x3a2c, 0, 0x04040404), - RCBA_RMW_REG_32(0x2b1c, 0, 0x03808033), - RCBA_RMW_REG_32(0x2b34, 0, 0x80000009), - RCBA_RMW_REG_32(0x3348, 0, 0x022ddfff), - RCBA_RMW_REG_32(0x334c, 0, 0x00000001), - RCBA_RMW_REG_32(0x3358, 0, 0x0001c000), - RCBA_RMW_REG_32(0x3380, 0, 0x3f8ddbff), - RCBA_RMW_REG_32(0x3384, 0, 0x0001c7e1), - RCBA_RMW_REG_32(0x338c, 0, 0x0001c7e1), - RCBA_RMW_REG_32(0x3398, 0, 0x0001c000), - RCBA_RMW_REG_32(0x33a8, 0, 0x00181900), - RCBA_RMW_REG_32(0x33dc, 0, 0x00080000), - RCBA_RMW_REG_32(0x33e0, 0, 0x00000001), - RCBA_RMW_REG_32(0x3a20, 0, 0x00000404), - RCBA_RMW_REG_32(0x3a24, 0, 0x01010101), - RCBA_RMW_REG_32(0x3a30, 0, 0x01010101), - RCBA_RMW_REG_32(0x0410, ~0, 0x00000003), - RCBA_RMW_REG_32(0x2618, ~0, 0x08000000), - RCBA_RMW_REG_32(0x2300, ~0, 0x00000002), - RCBA_RMW_REG_32(0x2600, ~0, 0x00000008), - RCBA_RMW_REG_32(0x33b4, 0, 0x00007001), - RCBA_RMW_REG_32(0x3350, 0, 0x022ddfff), - RCBA_RMW_REG_32(0x3354, 0, 0x00000001), - RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000), /* Power Optimizer */ - RCBA_RMW_REG_32(0x33c8, ~0, 0x08000080), /* Power Optimizer */ - RCBA_RMW_REG_32(0x2b10, 0, 0x0000883c), /* Power Optimizer */ - RCBA_RMW_REG_32(0x2b14, 0, 0x1e0a4616), /* Power Optimizer */ - RCBA_RMW_REG_32(0x2b24, 0, 0x40000005), /* Power Optimizer */ - RCBA_RMW_REG_32(0x2b20, 0, 0x0005db01), /* Power Optimizer */ - RCBA_RMW_REG_32(0x3a80, 0, 0x05145005), - RCBA_END_CONFIG +static const struct reg_script pch_misc_init_script[] = { + /* Setup SLP signal assertion, SLP_S4=4s, SLP_S3=50ms */ + REG_PCI_RMW16(GEN_PMCON_3, ~((3 << 4)|(1 << 10)), + (1 << 3)|(1 << 11)|(1 << 12)), + /* Prepare sleep mode */ + REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN), + /* Setup NMI on errors, disable SERR */ + REG_IO_RMW8(0x61, ~0xf0, (1 << 2)), + /* Disable NMI sources */ + REG_IO_OR8(0x70, (1 << 7)), + /* Indicate DRAM init done for MRC */ + REG_PCI_OR8(GEN_PMCON_2, (1 << 7)), + /* Enable BIOS updates outside of SMM */ + REG_PCI_RMW8(0xdc, ~(1 << 5), 0), + /* Clear status bits to prevent unexpected wake */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x3310, 0x00000031), + REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3f02, ~0x0000000f, 0), + /* Setup SERIRQ, enable continuous mode */ + REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)), +#if !CONFIG_SERIRQ_CONTINUOUS_MODE + REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0), +#endif + REG_SCRIPT_END }; -/* LynxPoint LP PCH Power Management init */ -static void lpt_lp_pm_init(struct device *dev) +/* Magic register settings for power management */ +static const struct reg_script pch_pm_init_script[] = { + REG_PCI_WRITE8(0xa9, 0x46), + REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x232c, ~1, 0), + REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1100, 0x0000c13f), + REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x2320, ~0x60, 0x10), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3314, 0x00012fff), + REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3318, ~0x000f0330, 0x0dcf0400), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3324, 0x04000000), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3368, 0x00041400), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3388, 0x3f8ddbff), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33ac, 0x00007001), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b0, 0x00181900), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33c0, 0x00060A00), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33d0, 0x06200840), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a28, 0x01010101), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a2c, 0x040c0404), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a9c, 0x9000000a), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b1c, 0x03808033), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b34, 0x80000009), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3348, 0x022ddfff), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x334c, 0x00000001), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3358, 0x0001c000), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3380, 0x3f8ddbff), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3384, 0x0001c7e1), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x338c, 0x0001c7e1), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3398, 0x0001c000), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33a8, 0x00181900), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33dc, 0x00080000), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33e0, 0x00000001), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a20, 0x0000040c), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a24, 0x01010101), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a30, 0x01010101), + REG_PCI_RMW32(0xac, ~0x00200000, 0), + REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0410, 0x00000003), + REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2618, 0x08000000), + REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2300, 0x00000002), + REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2600, 0x00000008), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b4, 0x00007001), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3350, 0x022ddfff), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3354, 0x00000001), + REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x08000000), + REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x08000080), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b10, 0x0000883c), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b14, 0x1e0a4616), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b24, 0x40000005), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b20, 0x0005db01), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a80, 0x05145005), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a84, 0x00001005), + REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x2fff2fb1), + REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x00008000), + REG_SCRIPT_END +}; + +static void pch_enable_mphy(void) { - struct southbridge_intel_lynxpoint_config *config = dev->chip_info; - u32 data; + u32 gpio71_native = gpio_is_native(71); + u32 data_and = 0xffffffff; + u32 data_or = (1 << 14) | (1 << 13) | (1 << 12); - printk(BIOS_DEBUG, "LynxPoint LP PM init\n"); + if (gpio71_native) { + data_or |= (1 << 0); + if (pch_is_wpt()) { + data_and &= ~((1 << 7) | (1 << 6) | (1 << 3)); + data_or |= (1 << 5) | (1 << 4); - pci_write_config8(dev, 0xa9, 0x46); + if (pch_is_wpt_ulx()) { + /* Check if SATA and USB3 MPHY are enabled */ + u32 strap19 = pch_read_soft_strap(19); + strap19 &= ((1 << 31) | (1 << 30)); + strap19 >>= 30; + if (strap19 == 3) { + data_or |= (1 << 3); + printk(BIOS_DEBUG, "Enable ULX MPHY PG " + "control in single domain\n"); + } else if (strap19 == 0) { + printk(BIOS_DEBUG, "Enable ULX MPHY PG " + "control in split domains\n"); + } else { + printk(BIOS_DEBUG, "Invalid PCH Soft " + "Strap 19 configuration\n"); + } + } else { + data_or |= (1 << 3); + } + } + } - pch_config_rcba(lpt_lp_pm_rcba); + pch_iobp_update(0xCF000000, data_and, data_or); +} - pci_write_config32(dev, 0xac, - pci_read_config32(dev, 0xac) | (1 << 21)); +/* Power Management init */ +static void pch_pm_init(struct device *dev) +{ + printk(BIOS_DEBUG, "PCH PM init\n"); + + pch_enable_mphy(); + + reg_script_run_on_dev(dev, pch_pm_init_script); + + if (pch_is_wpt()) + RCBA32_OR(0x33e0, (1 << 4) | (1 << 1)); - pch_iobp_update(0xED00015C, ~(1<<11), 0x00003700); - pch_iobp_update(0xED000118, ~0UL, 0x00c00000); - pch_iobp_update(0xED000120, ~0UL, 0x00240000); pch_iobp_update(0xCA000000, ~0UL, 0x00000009); - /* Set RCBA CIR28 0x3A84 based on SATA port enables */ - data = 0x00001005; - /* Port 3 and 2 disabled */ - if ((config->sata_port_map & ((1 << 3)|(1 << 2))) == 0) - data |= (1 << 24) | (1 << 26); - /* Port 1 and 0 disabled */ - if ((config->sata_port_map & ((1 << 1)|(1 << 0))) == 0) - data |= (1 << 20) | (1 << 18); - RCBA32(0x3a84) = data; - /* Set RCBA 0x2b1c[29]=1 if DSP disabled */ if (RCBA32(FD) & PCH_DISABLE_ADSPD) RCBA32_OR(0x2b1c, (1 << 29)); /* Lock */ RCBA32_OR(0x3a6c, 0x00000001); - - /* Set RCBA 0x33D4 after other setup */ - RCBA32_OR(0x33d4, 0x2fff2fb1); - - /* Set RCBA 0x33C8[15]=1 as last step */ - RCBA32_OR(0x33c8, (1 << 15)); } -static void enable_hpet(void) +static void pch_cg_init(device_t dev) { u32 reg32; - - /* Move HPET to default address 0xfed00000 and enable it */ - reg32 = RCBA32(HPTC); - reg32 |= (1 << 7); // HPET Address Enable - reg32 &= ~(3 << 0); - RCBA32(HPTC) = reg32; - /* Read it back to stick. It's affected by posted write syndrome. */ - reg32 = RCBA32(HPTC); -} - -static void enable_clock_gating(device_t dev) -{ - /* LynxPoint Mobile */ - u32 reg32; u16 reg16; /* DMI */ - RCBA32_AND_OR(0x2234, ~0UL, 0xf); + RCBA32_OR(0x2234, 0xf); + reg16 = pci_read_config16(dev, GEN_PMCON_1); - reg16 |= (1 << 11) | (1 << 12) | (1 << 14); + reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */ + if (pch_is_wpt()) + reg16 &= ~(1 << 11); + else + reg16 |= (1 << 11); + reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12); reg16 |= (1 << 2); // PCI CLKRUN# Enable pci_write_config16(dev, GEN_PMCON_1, reg16); - RCBA32_OR(0x900, (1 << 14)); - - reg32 = RCBA32(CG); - reg32 |= (1 << 22); // HDA Dynamic - reg32 |= (1 << 31); // LPC Dynamic - reg32 |= (1 << 16); // PCIe Dynamic - reg32 |= (1 << 27); // HPET Dynamic - reg32 |= (1 << 28); // GPIO Dynamic - RCBA32(CG) = reg32; - - RCBA32_OR(0x38c0, 0x7); // SPI Dynamic -} - -static void enable_lp_clock_gating(device_t dev) -{ - /* LynxPoint LP */ - u32 reg32; - u16 reg16; - - /* DMI */ - RCBA32_AND_OR(0x2234, ~0UL, 0xf); - reg16 = pci_read_config16(dev, GEN_PMCON_1); - reg16 &= ~((1 << 11) | (1 << 14)); - reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12) | (1 << 13); - reg16 |= (1 << 2); // PCI CLKRUN# Enable - pci_write_config16(dev, GEN_PMCON_1, reg16); - - reg32 = pci_read_config32(dev, 0x64); - reg32 |= (1 << 6); - pci_write_config32(dev, 0x64, reg32); /* * RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1 @@ -479,9 +351,9 @@ static void enable_lp_clock_gating(device_t dev) */ RCBA32_AND_OR(0x2614, 0x8bffffff, 0x0a206500); - /* Check for LPT-LP B2 stepping and 0:31.0@0xFA > 4 */ - if (pci_read_config8(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x8) >= 0x0b) - RCBA32_OR(0x2614, (1<<26)); + /* Check for 0:2.0@0x08 >= 0x0b */ + if (pci_read_config8(SA_DEV_IGD, 0x8) >= 0x0b) + RCBA32_OR(0x2614, (1 << 26)); RCBA32_OR(0x900, 0x0000031f); @@ -501,106 +373,51 @@ static void enable_lp_clock_gating(device_t dev) reg32 |= (1 << 16); // PCI Dynamic RCBA32(CG) = reg32; - RCBA32_OR(0x3434, 0x7); // LP LPC + /* PCH-LP LPC */ + if (pch_is_wpt()) + RCBA32_AND_OR(0x3434, ~0x1f, 0x17); + else + RCBA32_OR(0x3434, 0x7); - RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); // SATA + /* SATA */ + RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); - RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic + /* SPI */ + RCBA32_OR(0x38c0, 0x3c07); - pch_iobp_update(0xCF000000, ~0UL, 0x00007001); - pch_iobp_update(0xCE00C000, ~1UL, 0x00000000); // bit0=0 in BWG 1.4.0 + pch_iobp_update(0xCE00C000, ~1UL, 0x00000000); } static void pch_set_acpi_mode(void) { #if CONFIG_HAVE_SMI_HANDLER if (acpi_slp_type != 3) { -#if ENABLE_ACPI_MODE_IN_COREBOOT - printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); - outb(APM_CNT_ACPI_ENABLE, APM_CNT); - printk(BIOS_DEBUG, "done.\n"); -#else printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); -#endif } #endif /* CONFIG_HAVE_SMI_HANDLER */ } -static void pch_disable_smm_only_flashing(struct device *dev) -{ - u8 reg8; - - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - reg8 &= ~(1 << 5); - pci_write_config8(dev, 0xdc, reg8); -} - -static void pch_fixups(struct device *dev) -{ - u8 gen_pmcon_2; - - /* Indicate DRAM init done for MRC S3 to know it can resume */ - gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2); - gen_pmcon_2 |= (1 << 7); - pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2); - - /* - * Enable DMI ASPM in the PCH - */ - RCBA32_AND_OR(0x2304, ~(1 << 10), 0); - RCBA32_OR(0x21a4, (1 << 11)|(1 << 10)); - RCBA32_OR(0x21a8, 0x3); -} - static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "pch: lpc_init\n"); - - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); - - /* IO APIC initialization. */ - pch_enable_apic(dev); - - pch_enable_serial_irqs(dev); - - /* Setup the PIRQ. */ - pch_pirq_init(dev); - - /* Setup power options. */ - pch_power_options(dev); - - /* Initialize power management */ - if (pch_is_lp()) { - lpt_lp_pm_init(dev); - enable_lp_clock_gating(dev); - } else { - lpt_pm_init(dev); - enable_clock_gating(dev); - } - - /* Initialize the real time clock. */ - pch_rtc_init(dev); - - /* Initialize ISA DMA. */ + /* Legacy initialization */ isa_dma_init(); + pch_rtc_init(dev); + reg_script_run_on_dev(dev, pch_misc_init_script); - /* Initialize the High Precision Event Timers, if present. */ - enable_hpet(); - + /* Interrupt configuration */ + pch_enable_ioapic(dev); + pch_pirq_init(dev); setup_i8259(); - - /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - pch_disable_smm_only_flashing(dev); + /* Initialize power management */ + pch_power_options(dev); + pch_pm_init(dev); + pch_cg_init(dev); pch_set_acpi_mode(); - - pch_fixups(dev); } static void pch_lpc_add_mmio_resources(device_t dev) @@ -620,9 +437,9 @@ static void pch_lpc_add_mmio_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* RCBA */ - if (DEFAULT_RCBA < default_decode_base) { + if (RCBA_BASE_ADDRESS < default_decode_base) { res = new_resource(dev, RCBA); - res->base = DEFAULT_RCBA; + res->base = RCBA_BASE_ADDRESS; res->size = 16 * 1024; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_RESERVE; @@ -703,11 +520,11 @@ static void pch_lpc_add_io_resources(device_t dev) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* GPIOBASE */ - pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, - GPIO_BASE); + pch_lpc_add_io_resource(dev, GPIO_BASE_ADDRESS, + GPIO_BASE_SIZE, GPIO_BASE); /* PMBASE */ - pch_lpc_add_io_resource(dev, get_pmbase(), 256, PMBASE); + pch_lpc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, PMBASE); /* LPC Generic IO Decode range. */ pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC);