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broadwell: Add config option to disable DSP power gating in D3

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This is useful for debug and testing.

BUG=chrome-os-partner:29649
BRANCH=None
TEST=build and boot on samus

Change-Id: I9050e75fd7c308ebd97d196298c687f8b0f8f97d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210599
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2014-07-31 10:41:56 -07:00 • committed by chrome-internal-fetch
commit 2831154af4
2 changed files with 18 additions and 5 deletions
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20
src/soc/intel/broadwell/adsp.c
View file

@ -68,12 +68,22 @@ static void adsp_init(struct device *dev)
/* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */
tmp32 = pci_read_config32(dev, ADSP_PCI_VDRTCTL0);
if (pch_is_wpt()) {
tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT;
tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT;
if (config->adsp_d3_pg_disable) {
if (pch_is_wpt()) {
tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT;
tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT;
} else {
tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT;
tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT;
}
} else {
tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT;
tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT;
if (pch_is_wpt()) {
tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT;
tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT;
} else {
tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT;
tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT;
}
}
pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32);

3
src/soc/intel/broadwell/chip.h
View file

@ -84,6 +84,9 @@ struct soc_intel_broadwell_config {
uint8_t sio_i2c0_voltage;
uint8_t sio_i2c1_voltage;
/* Disable ADSP power gating in D3 */
uint8_t adsp_d3_pg_disable;
/*
* Clock Disable Map:
* [21:16] = CLKOUT_PCIE# 5-0