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UPSTREAM: soc/intel/common: Add save/restore for variable MRC data

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Piggy-back on existing MRC cache infrastructure to store variable MRC data.

Only one set of data can be valid at given point of time. Currently this
magically happens because region alignment is forced to 0x1000 and region
itself is of the same size. This needs to be somehow programmatically
enforced.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/17320
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I8a660d356ca760b8ff9907396fb9b34cb16cf1db
Reviewed-on: https://chromium-review.googlesource.com/415636
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Andrey Petrov 2016-11-08 08:30:06 -08:00 • committed by chrome-bot
commit 2818a29933
5 changed files with 96 additions and 31 deletions
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src/include/elog.h
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@ -160,6 +160,7 @@ struct elog_event_data_me_extended {
#define ELOG_TYPE_MEM_CACHE_UPDATE 0xaa
#define ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL 0
#define ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY 1
#define ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE 2
#define ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS 0
#define ELOG_MEM_CACHE_UPDATE_STATUS_FAIL 1
struct elog_event_mem_cache_update {