diff --git a/src/mainboard/intel/ptlrvp/mainboard.c b/src/mainboard/intel/ptlrvp/mainboard.c
index e14c5ace79..5b80d9d650 100644
--- a/src/mainboard/intel/ptlrvp/mainboard.c
+++ b/src/mainboard/intel/ptlrvp/mainboard.c
@@ -28,12 +28,15 @@ void __weak variant_update_soc_chip_config(struct soc_intel_pantherlake_config *
 static void mainboard_init(void *chip_info)
 {
 	struct pad_config *padbased_table;
-	const struct pad_config *base_pads;
-	size_t base_num;
+	const struct pad_config *base_pads, *variant_diff_pads;
+	size_t base_num, variant_diff_num;
 
 	padbased_table = new_padbased_table();
 	base_pads = variant_gpio_table(&base_num);
 	gpio_padbased_override(padbased_table, base_pads, base_num);
+	variant_diff_pads = variant_board_gpio_diff_table(&variant_diff_num);
+	if (variant_diff_pads)
+		gpio_padbased_override(padbased_table, variant_diff_pads, variant_diff_num);
 	fw_config_gpio_padbased_override(padbased_table);
 	gpio_configure_pads_with_padbased(padbased_table);
 	free(padbased_table);
diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
index 0ee09a5835..05ddf5bb5f 100644
--- a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
@@ -23,6 +23,7 @@ enum ptl_boardid {
  */
 
 const struct pad_config *variant_gpio_table(size_t *num);
+const struct pad_config *variant_board_gpio_diff_table(size_t *num);
 const struct pad_config *variant_early_gpio_table(size_t *num);
 const struct pad_config *variant_romstage_gpio_table(size_t *num);
 void fw_config_configure_pre_mem_gpio(void);
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c
index 9531065689..7b4dbe3c9f 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c
@@ -3,10 +3,11 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <boardid.h>
+#include <ec/intel/board_id.h>
 #include <soc/gpio.h>
 
 /* Pad configuration in ramstage*/
-static const struct pad_config gpio_table[] = {
+static const struct pad_config t3_gpio_table[] = {
 	/* GPP_A00:     ESPI_IO0_EC_R */
 	/*  GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
 
@@ -391,10 +392,48 @@ static const struct pad_config romstage_gpio_table[] = {
 	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
 };
 
+/* Pad difference in ramstage for LP5 T4 RVP */
+static const struct pad_config t4_gpio_diff_table[] = {
+	/* GPP_B09:     MOD_TCSS2_DISP_HPD1 */
+	PAD_CFG_NF(GPP_B09, NONE, DEEP, NF2),
+	/* GPP_B10:     MOD_TCSS1_DISP_HPD2 */
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF2),
+	/* GPP_B11:     GEN4_SSD_PWREN */
+	PAD_CFG_GPO(GPP_B11, 1, PLTRST),
+
+	/* GPP_B14:     Not used */
+	PAD_NC(GPP_B14, NONE),
+
+	/* GPP_B17:     MOD_TCSS2_LSX_DIR_SEL_EDP_VDD_EN */
+	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
+
+	/* GPP_C06:     X4_PCIE_SLOT_PWR_EN_N */
+	PAD_CFG_GPO(GPP_C06, 0, DEEP),
+	/* GPP_C07:     X4_DT_PCIE_RST_N */
+	PAD_CFG_GPO(GPP_C07, 1, DEEP),
+
+	/* GPP_D01:     MOD_TCSS2_TYP_A_VBUS_EN_EDP_BKLT_EN */
+	PAD_CFG_NF(GPP_D01, NONE, DEEP, NF2),
+	/* GPP_D02:     MOD_TCSS2_EDP_BKLT_CTRL */
+	PAD_CFG_NF(GPP_D02, NONE, DEEP, NF2),
+
+	/* GPP_D20:     CLKREQ7_X4_GEN5_DT_CEM_SLOT_N */
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+
+	/* GPP_E08:     M2_GEN4_SSD_RESET_N */
+	PAD_CFG_GPO(GPP_E08, 1, PLTRST),
+
+	/* GPP_F23:     SMC_LID */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F23, NONE, DEEP, LEVEL, ACPI),
+
+	/* GPP_V17:     TCP_RT_S0IX_ENTRY_EXIT_N */
+	PAD_CFG_GPO(GPP_V17, 1, PLTRST),
+};
+
 const struct pad_config *variant_gpio_table(size_t *num)
 {
-	*num = ARRAY_SIZE(gpio_table);
-	return gpio_table;
+	*num = ARRAY_SIZE(t3_gpio_table);
+	return t3_gpio_table;
 }
 
 const struct pad_config *variant_early_gpio_table(size_t *num)
@@ -410,6 +449,24 @@ const struct pad_config *variant_romstage_gpio_table(size_t *num)
 	return romstage_gpio_table;
 }
 
+const struct pad_config *variant_board_gpio_diff_table(size_t *num)
+{
+	int board_id = get_rvp_board_id();
+
+	switch (board_id) {
+	case PTLP_LP5_T3_RVP:
+		return NULL;
+	case PTLP_LP5_T4_RVP:
+		*num = ARRAY_SIZE(t4_gpio_diff_table);
+		return t4_gpio_diff_table;
+	case GCS_32GB:
+	case GCS_64GB:
+		return NULL;
+	default:
+		die("Unknown board ID = 0x%x\n", board_id);
+	}
+}
+
 static const struct cros_gpio cros_gpios[] = {
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME),
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),