dts needed to build.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@372 f3766cd6-281f-0410-b1cd-43a5c92072e9
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44
southbridge/amd/cs5536/dts
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44
southbridge/amd/cs5536/dts
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/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software = "0"; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation = "0"; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY = "0"; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program = "0"; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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{
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constructor = "cs5536_constructors";
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/* interrupt enables for LPC bus = "0"; each bit is an irq 0-15 */
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lpc_serirq_enable = "0";
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/* LPC IRQ polarity = "0"; each bit is an irq 0-15 */
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lpc_serirq_polarity = "0";
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/* 0:Continuous 1:Quiet */
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lpc_serirq_mode = "0";
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/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual pci spec... */
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enable_gpio_int_route = "0";
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/* 0:IDE 1:FLASH, if you are using nand flash instead of IDE drive */
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enable_ide_nand_flash = "0";
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/* Enable USB Port 4 0:host 1:device */
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enable_USBP4_device = "0";
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/* 0:off, xxxx:overcurrent setting, e.g. 0x3FEA CS5536 - Data Book (pages 380-381) */
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enable_USBP4_overcurrent = "0";
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com1_enable = "0";
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com1_address = "0x3f8";
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com1_irq = "4";
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com2_enable = "0";
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com2_address ="0x2f8";
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com2_irq = "3";
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};
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5
southbridge/intel/i82371eb/dts
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5
southbridge/intel/i82371eb/dts
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{
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ide0_enable = "0";
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ide1_enable = "0";
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constructor = "i82371eb_constructors";
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};
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