soc/qualcomm/ipq40xx: Add support for BLSP QUP I2C
Able to talk to the TPM device and the commands seem to succeed. BUG=chrome-os-partner:49249 chrome-os-partner:49250 TEST=All commands to the TPM succeed BRANCH=none Original-Commit-Id: c13900108f524c8422c38dee88469c8bfe24d0bd Original-Change-Id: Ie8c3c1ab1290cd8d7e6ddd1ae22f765c7be81019 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333314 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> squashed: soc/qualcomm/ipq40xx: Add support for BLSP QUP SPI - Enable BLSP SPI driver for ipq40xx - supports only FIFO mode BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: 0714025975854dd048d35fe602824ead4c7d94e9 Original-Change-Id: If809b0fdf7d6c9405db6fd3747a3774c00ea9870 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333303 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ia518af5bfc782b08a0883ac93224d476d07e2426 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14677 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Varadarajan Narayanan
Patrick Georgi
parent
3939acaa77
commit
2596764f34
19 changed files with 1076 additions and 1205 deletions
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@ -56,7 +56,7 @@ config DRAM_SIZE_MB
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config DRIVER_TPM_I2C_BUS
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hex
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default 0x1
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default 0x2
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config DRIVER_TPM_I2C_ADDR
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hex
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@ -21,7 +21,7 @@ bootblock-y += reset.c
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verstage-y += boardid.c
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verstage-y += cdp.c
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verstage-y += chromeos.c
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verstage-y += gsbi.c
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verstage-y += blsp.c
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verstage-y += memlayout.ld
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verstage-y += reset.c
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@ -27,34 +27,47 @@
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* SUCH DAMAGE.
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*/
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#include <gpio.h>
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#include <soc/gpio.h>
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#include <soc/gsbi.h>
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#include <soc/blsp.h>
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#include <soc/qup.h>
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#define GPIO_FUNC_I2C 0x1
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#define IPQ40XX_I2C0_PINGROUP_1 1
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#define IPQ40XX_I2C0_PINGROUP_2 (!IPQ40XX_I2C0_PINGROUP_1)
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int gsbi_init_board(gsbi_id_t gsbi_id)
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#if IPQ40XX_I2C0_PINGROUP_1
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#define SCL_GPIO 20
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#define SDA_GPIO 21
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#define GPIO_FUNC_SCL 0x1
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#define GPIO_FUNC_SDA 0x1
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#elif IPQ40XX_I2C0_PINGROUP_2
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#define SCL_GPIO 58
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#define SDA_GPIO 59
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#define GPIO_FUNC_SCL 0x3
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#define GPIO_FUNC_SDA 0x2
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#else
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#warning "TPM: I2C pingroup not specified"
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#endif
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int blsp_i2c_init_board(blsp_qup_id_t id)
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{
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switch (gsbi_id) {
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case GSBI_ID_7:
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gpio_tlmm_config_set(8, GPIO_FUNC_I2C,
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GPIO_NO_PULL, GPIO_2MA, 1);
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gpio_tlmm_config_set(9, GPIO_FUNC_I2C,
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GPIO_NO_PULL, GPIO_2MA, 1);
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break;
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case GSBI_ID_4:
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/* Configure GPIOs 13 - SCL, 12 - SDA, 2mA gpio_en */
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gpio_tlmm_config_set(12, GPIO_FUNC_I2C,
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GPIO_NO_PULL, GPIO_2MA, 1);
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gpio_tlmm_config_set(13, GPIO_FUNC_I2C,
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GPIO_NO_PULL, GPIO_2MA, 1);
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break;
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case GSBI_ID_1:
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/* Configure GPIOs 54 - SCL, 53 - SDA, 2mA gpio_en */
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gpio_tlmm_config_set(54, GPIO_FUNC_I2C,
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GPIO_NO_PULL, GPIO_2MA, 1);
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gpio_tlmm_config_set(53, GPIO_FUNC_I2C,
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GPIO_NO_PULL, GPIO_2MA, 1);
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switch (id) {
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case BLSP_QUP_ID_0:
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case BLSP_QUP_ID_1:
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case BLSP_QUP_ID_2:
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case BLSP_QUP_ID_3:
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#if defined(IPQ40XX_I2C0_PINGROUP_1) || defined(IPQ40XX_I2C0_PINGROUP_2)
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gpio_tlmm_config_set(SDA_GPIO, GPIO_FUNC_SDA,
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GPIO_NO_PULL, GPIO_2MA, 1);
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gpio_tlmm_config_set(SCL_GPIO, GPIO_FUNC_SCL,
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GPIO_NO_PULL, GPIO_2MA, 1);
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#endif /* Pin Group 1 or 2 */
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break;
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default:
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return 1;
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@ -20,7 +20,7 @@
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#include <drivers/i2c/ww_ring/ww_ring.h>
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#include <gpio.h>
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#include <soc/cdp.h>
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#include <soc/gsbi.h>
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#include <soc/blsp.h>
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#include <string.h>
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#include <timer.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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@ -22,6 +22,7 @@
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#include <soc/clock.h>
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#include <soc/soc_services.h>
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#include <soc/usb.h>
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#include <soc/blsp.h>
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#include <symbols.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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@ -37,7 +38,7 @@ static void setup_usb(void)
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}
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#define TPM_RESET_GPIO 19
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static void ipq_setup_tpm(void)
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void ipq_setup_tpm(void)
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{
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#ifdef CONFIG_I2C_TPM
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gpio_tlmm_config_set(TPM_RESET_GPIO, FUNC_SEL_GPIO,
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