From 255fcb14ba02061d8853bdd4d9060bf0009e4253 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sun, 1 Feb 2026 10:02:46 +0100 Subject: [PATCH] sb/intel/bd82x6x/lpc: Advertise all fixed MMIO ranges Currently not all fixed MMIO ranges are advertised to the resource allocator. This is not an issue as long bottom-up allocation is used and as long as only small PCI BARs are present on the system. Properly advertise all fixed MMIO ranges decoded by the PCH: - RCBA - TXT private - TXT reserved - TPM TIS - LGMR - HPET Also remove subtractive decoding from IOAPIC and SPI ROM. Comments indicate that there's an issue with the OS, but newer platforms also don't set it to subtractive. No issue was seen with EDK2 payload and Linux 6.8.8. As a side effect IOAPIC and SPI ROM are now marked as reserved in e820, which should help payloads not aware of IOAPIC and SPI ROM to behave more properly. TEST=Still boots on Lenovo X220. No issues seen in coreboot or Linux. New e820 reserved ranges: [DEBUG] 15. 00000000fec00000-00000000fec00fff: RESERVED [DEBUG] 16. 00000000fed00000-00000000fed00fff: RESERVED [DEBUG] 18. 00000000fed1c000-00000000fed3ffff: RESERVED [DEBUG] 19. 00000000fed45000-00000000fed91fff: RESERVED [DEBUG] 20. 00000000ff000000-00000000ffffffff: RESERVED Change-Id: I9c251a8c4a4403c5dc0ad535769d8d893dc64a05 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/91040 Tested-by: build bot (Jenkins) Reviewed-by: Alicja Michalska Reviewed-by: Paul Menzel --- src/southbridge/intel/bd82x6x/lpc.c | 56 ++++++++++++++++++++++++++--- 1 file changed, 52 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 67d883ad48..cdd1bb3f11 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -560,19 +561,66 @@ static void pch_lpc_read_resources(struct device *dev) res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); + res = new_resource(dev, 2); res->base = 0xff000000; /* Some systems (e.g. X230) have 12 MiB flash. SPI controller supports up to 2 x 16 MiB of flash but address map limits this to 16MiB. */ res->size = 0x01000000; /* 16 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | + IORESOURCE_FIXED | IORESOURCE_RESERVE; res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | + IORESOURCE_FIXED | IORESOURCE_RESERVE; + + /* HPET */ + res = new_resource(dev, 4); + res->base = (resource_t)HPET_BASE_ADDRESS; + res->size = 4 * KiB; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | + IORESOURCE_FIXED | IORESOURCE_RESERVE; + + /* TXT_PRIVATE_SPACE */ + res = new_resource(dev, 5); + res->base = (resource_t)0xfed20000; + res->size = 0x20000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | + IORESOURCE_FIXED | IORESOURCE_RESERVE; + + /* Misc ICH + TXT_RESERVED_SPACE */ + res = new_resource(dev, 6); + res->base = (resource_t)0xfed45000; + res->size = 0x4b000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | + IORESOURCE_FIXED | IORESOURCE_RESERVE; + + /* RCBA */ + res = new_resource(dev, RCBA); + res->base = (resource_t)CONFIG_FIXED_RCBA_MMIO_BASE; + res->size = CONFIG_RCBA_LENGTH; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | + IORESOURCE_FIXED | IORESOURCE_RESERVE; + + /* LPC TPM TIS */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); + res->base = 0xfed40000; + res->size = 0x00005000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + /* Check LPC Memory Decode register. */ + u32 reg = pci_read_config32(dev, LGMR); + if (reg & 1) { + reg &= ~0xffff; + res = new_resource(dev, LGMR); + res->base = reg; + res->size = 64 * 1024; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | + IORESOURCE_FIXED | IORESOURCE_RESERVE; + } /* Set PCH IO decode ranges if required.*/ if ((config->gen1_dec & 0xFFFC) > 0x1000) {