From 24d8e6f35e1d22b50602b202d16255115160f87e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 30 Apr 2025 14:18:07 +0200 Subject: [PATCH] Revert "mb/google/brox: Handle GPI_INT pin lower to GPI_WAKE" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This partially reverts commit 32ebaef73c8e ("mb/google/brox: Handle GPI_INT pin lower to GPI_WAKE") as google/brox board has moved away from the PAD_CFG_GPI_INT_SWAPPED usage. The revert simply removes the PAD_CFG_GPI_INT_SWAPPED solution, which is not used anywhere anymore. PAD_CFG0_ROUTE_SWAPPED bit can not be found in any PCH datasheet nor EDS. Furthermore, the definition conflicts with PAD_CFG0_NAFVWE_ENABLE bit, which, on the contrary, is defined in the datasheets and PCH EDS. The conflict results in boards printing: "GPIO XX doesn't support APIC routing," (where XX is pad number) for each pad having the NAFVWE bit set. Currently, none of the boards use PAD_CFG0_ROUTE_SWAPPED bit, and due to the bit field conflict I assume it was mistakenly added. Change-Id: I71299c9729f294cfafaec02222ef01e96b575740 Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/87485 Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel --- src/soc/intel/common/block/gpio/gpio.c | 6 ++---- .../block/include/intelblocks/gpio_defs.h | 21 ------------------- 2 files changed, 2 insertions(+), 25 deletions(-) diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 625c3f4355..d74e01da62 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -294,8 +294,7 @@ static void gpio_configure_itss(const struct pad_config *cfg, uint16_t port, * in the GPIO pad configuration so that a hardware active low * signal looks that way to the APIC (double inversion). */ - if (!(cfg->pad_config[0] & PAD_CFG0_ROUTE_SWAPPED) && - !(cfg->pad_config[0] & PAD_CFG0_ROUTE_IOAPIC)) + if (!(cfg->pad_config[0] & PAD_CFG0_ROUTE_IOAPIC)) return; irq = pcr_read32(port, PAD_CFG1_OFFSET(pad_cfg_offset)); @@ -306,8 +305,7 @@ static void gpio_configure_itss(const struct pad_config *cfg, uint16_t port, return; } - if (CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG) && - !(cfg->pad_config[0] & PAD_CFG0_ROUTE_SWAPPED)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG)) itss_set_irq_polarity(irq, !!(cfg->pad_config[0] & PAD_CFG0_RX_POL_INVERT)); diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index bcf8e73f7e..411b1acca1 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -44,7 +44,6 @@ #define PAD_CFG0_ROUTE_SMI (1 << 18) #define PAD_CFG0_ROUTE_SCI (1 << 19) #define PAD_CFG0_ROUTE_IOAPIC (1 << 20) -#define PAD_CFG0_ROUTE_SWAPPED (1 << 27) #define PAD_CFG0_RXTENCFG_MASK (3 << 21) #define PAD_CFG0_RXINV_MASK (1 << 23) #define PAD_CFG0_RX_POL_INVERT (1 << 23) @@ -337,26 +336,12 @@ PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) -#define PAD_CFG_GPI_TRIG_OWN_SWAPPED(pad, pull, rst, trig, own) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_ROUTE(SWAPPED), \ - PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) - #define PAD_CFG_GPI_TRIG_OWN_LOCK(pad, pull, rst, trig, own, lock_action) \ _PAD_CFG_STRUCT_LOCK(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own), PAD_LOCK(lock_action)) -#define PAD_CFG_GPI_TRIG_OWN_LOCK_SWAPPED(pad, pull, rst, trig, own, lock_action) \ - _PAD_CFG_STRUCT_LOCK(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_ROUTE(SWAPPED), \ - PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own), PAD_LOCK(lock_action)) - #define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ @@ -385,16 +370,10 @@ #define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, DRIVER) -#define PAD_CFG_GPI_INT_SWAPPED(pad, pull, rst, trig) \ - PAD_CFG_GPI_TRIG_OWN_SWAPPED(pad, pull, rst, trig, DRIVER) - /* GPIO Interrupt with lock */ #define PAD_CFG_GPI_INT_LOCK(pad, pull, trig, lock_action) \ PAD_CFG_GPI_TRIG_OWN_LOCK(pad, pull, PWROK, trig, DRIVER, lock_action) -#define PAD_CFG_GPI_INT_LOCK_SWAPPED(pad, pull, trig, lock_action) \ - PAD_CFG_GPI_TRIG_OWN_LOCK_SWAPPED(pad, pull, PWROK, trig, DRIVER, lock_action) - /* Bidirectional GPIO port when both RX and TX buffer is enabled */ #define PAD_CFG_GPIO_BIDIRECT_IOS(pad, val, pull, rst, trig, iosstate, iosterm, own) \ _PAD_CFG_STRUCT(pad, \