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more BCM CMOS menu stuff

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This commit is contained in:
Li-Ta Lo 2002-07-22 03:08:25 +00:00
commit 24b6351c3e
4 changed files with 355 additions and 15 deletions
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349
src/mainboard/bcm/e100/ipl.S
View file

@ -58,6 +58,322 @@ lpc_init_start: # inits LPC bridge for accessing
lpc_init_complete:
SET_VGA_SR13:
movw $0x03c4,%dx #SR5
movb $0x05,%al
outb %al,%dx
movw $0x03c5,%dx #Enable
movb $0x86,%al
outb %al,%dx
movw $0x0070,%dx
movb $0x51,%al #SR13
outb %al,%dx
movw $0x0071,%dx
inb %dx,%al
movb %al,%bl
andb $0xc0,%al
cmpb $0x80,%al
jne SET_VGA_SR14
movw $0x03c4,%dx
movb $0x13,%al
outb %al,%dx
movw $0x03c5,%dx
movb %bl,%al
andb $0x3f,%al
outb %al,%dx
SET_VGA_SR14:
movw $0x0070,%dx
movb $0x71,%al #SR14
outb %al,%dx
movw $0x0071,%dx
inb %dx,%al
movb %al,%bl
andb $0x3f,%al
cmpb $0x0f,%al
jg SET_VGA_SR16
movw $0x03c4,%dx
movb $0x14,%al
outb %al,%dx
movw $0x03c5,%dx
movb %bl,%al
outb %al,%dx
SET_VGA_SR16:
movw $0x0070,%dx
movb $0x61,%al #SR16
outb %al,%dx
movw $0x0071,%dx
inb %dx,%al
movb %al,%bl
movw $0x03c4,%dx
movb $0x16,%al
outb %al,%dx
movw $0x03c5,%dx
movb %bl,%al
outb %al,%dx
SET_VGA_COMPLETE:
movw $0x0080,%dx
movb $1,%al
outb %al,%dx
//Get Base Address
movw $0xcf8,%dx
movl $0x80000874,%eax
outl %eax,%dx
movw $0xcfc,%dx
inl %dx,%eax
movw %ax,%dx
//Disable Watch Dog Timer
addw $0x4b,%dx #set 0x4b=0x00
movb $0x00,%al
outb %al,%dx
movw $0x0080,%dx
movb $2,%al
outb %al,%dx
//Increse The Retry Counter
movw $0x0070,%dx
movb $0x60,%al
outb %al,%dx
movw $0x0071,%dx
inb %dx,%al
addb $1,%al
outb %al,%dx
Clock_Gen:
//Get Complete Flag & Parameter
movw $0x0070,%dx
movb $0x50,%al
outb %al,%dx
movw $0x0071,%dx
inb %dx,%al
movb %al,%bl
andb $0x01,%al
cmpb $1,%al
jne Clock_Gen_Backup
movb %bl,%al
andb $0x08,%al
cmpb $0x08,%al
jne Clock_Gen_Backup
movb $0,%al
movb %al,%bl
Clock_Gen_Backup:
movw $0x0080,%dx
movb $3,%al
outb %al,%dx
//backup the parameter
movb %bl,%al
andb $0x02,%al
cmpb $0x02,%al
je Clock_Gen_Exit
Clock_Gen_Adjust:
//Get The Retry Counter
movw $0x0070,%dx
movb $0x60,%al
outb %al,%dx
movw $0x0071,%dx
inb %dx,%al
cmpb $3,%al //It can try 2 times
jl Clock_Gen_Start
//Clear The Retry Counter
movw $0x0070,%dx
movb $0x60,%al
outb %al,%dx
movb $0,%al
movw $0x0071,%dx
outb %al,%dx
movb $0,%al #degrade to default
//Backup The New Parameter
movb %al,%bl
Clock_Gen_Start:
movw $0x0080,%dx
movb $4,%al
outb %al,%dx
//Restor The Parameter
movw $0x0070,%dx
movb $0x50,%al
outb %al,%dx
movb %bl,%al
movw $0x0071,%dx
outb %al,%dx
//Get Base Address
movw $0xcf8,%dx
movl $0x80000874,%eax
outl %eax,%dx
movw $0xcfc,%dx
inl %dx,%eax
movw %ax,%dx
//Set Clock
addw $0x83,%dx #set 0x83=0x20 KILL Operation
movb $0x20,%al
outb %al,%dx
addw $1,%dx #set 0x84=0xd2,Salve=0xd2 Write operation
movb $0xd2,%al
outb %al,%dx
addw $3,%dx #set 0x87=1 , ByteCount=1
movb $1,%al
outb %al,%dx
addw $1,%dx #set 0x88=clock
movb %bl,%al
andb $0xf4,%al
orb $0x08,%al #Clock Set by Software
outb %al,%dx
subw $5,%dx #set 0x83=0x05, Block write
movb $5,%al
outb %al,%dx
movb $0x15,%al #set 0x83=0x15, Start Block Write
outb %al,%dx
movw $0x0080,%dx
movb $5,%al
outb %al,%dx
//Get Base Address
movw $0xcf8,%dx
movl $0x80000874,%eax
outl %eax,%dx
movw $0xcfc,%dx
inl %dx,%eax
movw %ax,%dx
addw $0x80,%dx
movw $0xffff,%cx
Clock_Gen_Wait:
inb %dx,%al
andb $0x08,%al
cmpb $0x08,%al
je Clock_Gen_Complete
loop Clock_Gen_Wait
Clock_Gen_Fail:
movw $0x0080,%dx
movb $6,%al
outb %al,%dx
//Get Base Address
movw $0xcf8,%dx
movl $0x80000874,%eax
outl %eax,%dx
movw $0xcfc,%dx
inl %dx,%eax
movw %ax,%dx
//Set Watch Dog Timer(200 ms)
addw $0x4a,%dx #set 0x4a=50
movb $50,%al
outb %al,%dx
addw $1,%dx #set 0x4b=0x83
movb $0x83,%al
outb %al,%dx
movw $0x0080,%dx
movb $7,%al
outb %al,%dx
Clock_Gen_Delay1:
nop
jmp Clock_Gen_Delay1
Clock_Gen_Complete:
//Set the Complete Flag
movw $0x0070,%dx
movb $0x50,%al
outb %al,%dx
movw $0x0071,%dx
inb %dx,%al
orb $0x02,%al
outb %al,%dx
movw $0x0080,%dx
movb $8,%al
outb %al,%dx
//Get Base Address
movw $0xcf8,%dx
movl $0x80000874,%eax
outl %eax,%dx
movw $0xcfc,%dx
inl %dx,%eax
movw %ax,%dx
//Set Watch Dog Timer(200 ms)
addw $0x4a,%dx #set 0x4a=50
movb $50,%al
outb %al,%dx
addw $1,%dx #set 0x4b=0x83
movb $0x83,%al
outb %al,%dx
movw $0x0080,%dx
movb $9,%al
outb %al,%dx
Clock_Gen_Delay2:
nop
jmp Clock_Gen_Delay2
Clock_Gen_Exit:
//Clear the Complete Flag
movw $0x0070,%dx
movb $0x50,%al
outb %al,%dx
movw $0x0071,%dx
inb %dx,%al
andb $0xfd,%al
outb %al,%dx
//Clear The Retry Counter
movw $0x0070,%dx
movb $0x60,%al
outb %al,%dx
movb $0,%al
movw $0x0071,%dx
outb %al,%dx
movw $0x0080,%dx
movb $0x10,%al
outb %al,%dx
movw $0x5501, %ax # MDOE# enable, this bit
CALL_SP(write_pci_register) # should be set before sizing.
@ -75,17 +391,40 @@ eb_100:
movw $0x6006, %ax # GPIO7 == 1 ==> EB-100
CALL_SP(write_pci_register) # 2x12x9 (64MB)
movw $0x63a1, %ax # enable DIMM 0, SMA 8MB
CALL_SP(write_pci_register) # write register 0x63
// movw $0x63a1, %ax # enable DIMM 0, SMA 8MB
// CALL_SP(write_pci_register) # write register 0x63
jmp gpio_trap_end
jmp set_sma
eb_200:
movw $0x6002, %ax # GPIO7 == 0 ==> EB-200
CALL_SP(write_pci_register) # 2x12x8 (32MB)
movw $0x6391, %ax # enable DIMM 0, SMA 4MB
CALL_SP(write_pci_register) # write register 0x63
// movw $0x6391, %ax # enable DIMM 0, SMA 4MB
// CALL_SP(write_pci_register) # write register 0x63
set_sma:
//set share memory
movb $0x63, %ah # enable DIMM 0 and
movw $0x0070,%dx
movb $0x70,%al
outb %al,%dx
movw $0x0071,%dx
inb %dx,%al
andb $0x70,%al
cmpb $0x70,%al #Not supported yet
jne CHECK_NEXT
movb $0x20,%al #8MB
jmp CHECK_OK
CHECK_NEXT:
cmpb $0x60,%al #Not supported yet
jne CHECK_OK
movb $0x20,%al #8MB
CHECK_OK:
orb $0x81,%al
CALL_SP(write_pci_register) # write register 0x63
gpio_trap_end:
/* -----------------------------------------------------------------------------------------*/

8
src/mainboard/bcm/e100/mainboard.c
View file

@ -65,11 +65,13 @@ void
winbond_83697_init(void)
{
printk_info("Setting 2E ports.......\n");
outb(0x87, BASE);
outb(0x87, BASE);
outb(0x2c,BASE);
outb(0x55,BASE+1);
/* URA */
outb(0x2c, BASE);
outb(0x55, BASE+1);
/* URA */
outb(0x07, BASE);
outb(0x02, BASE+1);
outb(0x30, BASE);

2
src/northsouthbridge/sis/550/raminit.inc
View file

@ -66,7 +66,7 @@ write_common:
loopnz init_northbridge
#ifdef DISABLE_INTERNAL_DEVICES
movw $0x7c07, %ax # Writting undocumented LPC register
movw $0x7c02, %ax # Writting undocumented LPC register
write_lpc_register:
/* Input: AH - register number. AL - register value. */
movl $LPC_BRIDGE_BASE_ADDR, %edx

11
src/northsouthbridge/sis/550/southbridge.c
View file

@ -54,8 +54,8 @@ static const initreg_t ide_init[] = {
{ WORD, 0x2C, 0x00, 0x1039 }, /* Subsystem vendor ID. */
{ WORD, 0x2E, 0x00, 0x5513 }, /* Subsystem ID. */
{ BYTE, 0x3c, 0x00, 0x0e }, /* reserved don't do this, sets irq 14 */
{ BYTE, 0x40, 0x00, 0x04 }, /* Primary master data recovery time. 4 PCICLK */
{ BYTE, 0x41, 0x00, 0xb4 }, /* Primary master data active time. UDMA Mode 2 */
{ BYTE, 0x40, 0x00, 0x00 }, /* Primary master data recovery time. 4 PCICLK */
{ BYTE, 0x41, 0x00, 0xb0 }, /* Primary master data active time. UDMA Mode 2 */
{ BYTE, 0x42, 0x00, 0x00 }, /* Primary slave data recovery time. */
{ BYTE, 0x43, 0x00, 0x00 }, /* Primary slave data active time. */
{ BYTE, 0x44, 0x00, 0x00 }, /* Secondary master data recovery time. */
@ -136,14 +136,14 @@ void nvram_on()
/* turn on sis550 nvram. */
pcidev = pci_find_device(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, (void *)NULL);
if (pcidev != NULL) {
u8 data;
/* Enable FFF80000 to FFFFFFFF decode. You have to also enable
PCI Posted write for devices on sourthbridge */
pci_write_config_byte(pcidev, 0x40, 0x33);
/* Flash can be flashed, enable USB device in undocumented Bit 6 */
pci_write_config_byte(pcidev, 0x45, 0x60);
/* Enable USB device in undocumented Bit 5 */
pci_write_config_byte(pcidev, 0x45, 0x20);
}
//#if !defined(STD_FLASH)
/* turn off nvram shadow in 0xc0000 ~ 0xfffff, i.e. accessing segment C - F
is actually to the DRAM not NVRAM. For 512KB NVRAM case, this one should be
disabled */
@ -156,7 +156,6 @@ void nvram_on()
printk_debug("Shadow memory disabled in SiS 550\n");
}
//#endif
}
/* serial_irq_fixup: Enable Serial Interrupt. Serial interrupt is the IRQ line from SiS 950