From 2496943b5c04767639b2193d4f1a2d2fe9270455 Mon Sep 17 00:00:00 2001 From: Ren Kuo Date: Mon, 9 Dec 2024 12:26:48 +0800 Subject: [PATCH] mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2 Currently, with default speed auto the Wifi 7 M.2 module will not work under speed Gen3. This is due to driver iwlwifi for wifi7 is not stable and decreasing the speed to Gen2 gets the card working without any downsides, as the Wifi 7 speed can be serviced by 5 GT/s. BUG=b:376156567 TEST=Boot to OS and then check link speed. Use command: lspci -s 02:00.0 -vv | grep 'LnkSta' Before LnkSta: Speed 8GT/s (downgraded), Width x1 After LnkSta: Speed 5GT/s (downgraded), Width x1 Change-Id: I9e8a02061251f73ee5ec2299e62fa423ff4b0965 Signed-off-by: Ren Kuo Reviewed-on: https://review.coreboot.org/c/coreboot/+/85533 Reviewed-by: Subrata Banik Reviewed-by: David Wu Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/mainboard/google/brox/variants/jubilant/overridetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb index 880b3dd057..4e554ab23a 100644 --- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb +++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb @@ -294,6 +294,7 @@ chip soc/intel/alderlake .clk_src = 1, .clk_req = 1, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_pcie_speed = SPEED_GEN2, }" chip drivers/wifi/generic register "wake" = "GPE0_DW0_03"