From 243e969673aa9a19b72e117123c65af5c46a3b36 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Mon, 11 Aug 2008 23:07:19 +0000 Subject: [PATCH] I am self-acking the change to Kconfig because it is trivial. Signed-off-by: Ronald G. Minnich Acked-by: Ronald G. Minnich The other changes are: Acked-by: Carl-Daniel Hailfinger I am well aware that those defines are not a great idea. I need some good advice. I think we ought to have a stage1lib.c or something but I'll take suggestions. Thanks again git-svn-id: svn://coreboot.org/repository/coreboot-v3@746 f3766cd6-281f-0410-b1cd-43a5c92072e9 --- arch/x86/Kconfig | 19 +++++++++++++++++++ arch/x86/Makefile | 3 ++- arch/x86/resourcemap.c | 41 +++++++++++++++++++++++++---------------- 3 files changed, 46 insertions(+), 17 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index d5f380831a..f04413e7eb 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -124,12 +124,19 @@ config PIRQ_TABLE config SMP boolean + default 0 help This option is used to enable certain functions to make coreboot work correctly on symmetric multi processor systems. It is usually set in mainboard/*/Kconfig. +config IOAPIC + boolean + default 0 + help + If you want to configure an IOAPIC, set this. + config CARBASE hex default 0x8f000 if CPU_I586 @@ -192,3 +199,15 @@ config HT_FREQ_800MHZ help Can we run HT at 800 Mhz +config USBDEBUG_DIRECT + boolean + default 0 + help + Determines if we enable USB Direct debugging. If you don't have a dongle, + this is probably of no value to you. + +config APIC_ID_OFFSET + hex "APIC ID offset" + default 0x10 + help + This is entirely mainboard dependent. 0x10 is a *typical* setting but not always a good setting. diff --git a/arch/x86/Makefile b/arch/x86/Makefile index efe67681d7..ef5ea883a3 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -109,7 +109,8 @@ $(obj)/coreboot.bootblock: $(obj)/coreboot.vpd $(obj)/stage0.init STAGE0_LIB_OBJ = uart8250.o mem.o lar.o delay.o vtxprintf.o \ vsprintf.o console.o string.o $(DECOMPRESSORS) STAGE0_ARCH_X86_OBJ = stage1.o serial.o speaker.o \ - udelay_io.o mc146818rtc.o post_code.o + udelay_io.o mc146818rtc.o post_code.o \ + pci_ops_conf1.o resourcemap.o ifeq ($(CONFIG_PAYLOAD_ELF_LOADER),y) STAGE0_LIB_OBJ += elfboot.o diff --git a/arch/x86/resourcemap.c b/arch/x86/resourcemap.c index 6feb489e79..deac46d15b 100644 --- a/arch/x86/resourcemap.c +++ b/arch/x86/resourcemap.c @@ -17,7 +17,16 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include /** * setup a resource map. * for PCRM entries, add a pci device offset, and a pci "OR value offset" @@ -38,10 +47,10 @@ /* NOTE: By doing the config write in this manner we guarantee that this * will work in stage1 or stage2. */ -#define pci_read_config32(bus, dev, where) pci_cf8_conf1.read32(NULL, r->pcm.bus, dev, where) -#define pci_write_config32(bus, dev, where, what) pci_cf8_conf1.write32(NULL, r->pcm.bus, dev, where, what) +#define pci_read_config32(busdevfn, where) pci_cf8_conf1.read32(busdevfn, where) +#define pci_write_config32(busdevfn, where, what) pci_cf8_conf1.write32(busdevfn, where, what) -void setup_resource_map_x_offset(const rmap *rm, u32 max, +void setup_resource_map_x_offset(const struct rmap *rm, u32 max, u32 offset_bdf, u32 offset_pciio, u32 offset_io) { @@ -60,7 +69,7 @@ void setup_resource_map_x_offset(const rmap *rm, u32 max, #warning make sure offset_bus is right for extended PCI addressing u32 offset_bus = offset_bdf >> 8; printk(BIOS_DEBUG, "(%x+%x,%x+%x,%x+%x,%x) & %08x | %08x+%08x\n", rm->pcm.bus, - offset_bus, rm->pcm.dev+offset_devfn>>3, + offset_bus, rm->pcm.dev, (offset_devfn>>3), rm->pcm.fn, offset_devfn&3, rm->pcm.reg, rm->pcm.and,rm->pcm.or, offset_pciio); dev = rm->pcm.dev; @@ -68,21 +77,21 @@ void setup_resource_map_x_offset(const rmap *rm, u32 max, dev <<= 3; dev |= rm->pcm.fn; dev += offset_devfn; - reg = pci_read_config32(rm->pcm.bus + offset_bus, dev, where); + reg = pci_read_config32(PCI_BDEVFN(rm->pcm.bus + offset_bus, dev), where); reg &= rm->pcm.and; reg |= rm->pcm.or + offset_pciio; - pci_write_config32(rm->pcm.bus, dev, where, reg); + pci_write_config32(PCI_BDEVFN(rm->pcm.bus + offset_bus, dev), where, reg); } break; case TIO8: { u32 where; u8 reg; - printk(BIOS_DEBUG, "(%04x+%04x) & %02x | %02xx\n", rm->port, offset_io, rm->pcm.and,rm->pcm.or); - where = rm->port + offset_io; + printk(BIOS_DEBUG, "(%04x+%04x) & %02x | %02xx\n", rm->io8.port, offset_io, rm->io8.and,rm->io8.or); + where = rm->io8.port + offset_io; reg = inb(where); - reg &= rm->and; - reg |= rm->or; + reg &= rm->io8.and; + reg |= rm->io8.or; outb(reg, where); } break; @@ -90,11 +99,11 @@ void setup_resource_map_x_offset(const rmap *rm, u32 max, { u32 where; u32 reg; - printk(BIOS_DEBUG, "(%04x+%04x) & %02x | %02xx\n", rm->port, offset_io, rm->pcm.and,rm->pcm.or); - where = rm->port + offset_io; + printk(BIOS_DEBUG, "(%04x+%04x) & %02x | %02xx\n", rm->io32.port, offset_io, rm->io32.and,rm->io32.or); + where = rm->io32.port + offset_io; reg = inl(where); - reg &= rm->and; - reg |= rm->or; + reg &= rm->io32.and; + reg |= rm->io32.or; outl(reg, where); } break; @@ -116,6 +125,6 @@ void setup_resource_map_x_offset(const rmap *rm, u32 max, void setup_resource_map(const struct rmap *rm, u32 max) { - setup_resource_map_x_offset(rm, max); + setup_resource_map_x_offset(rm, max, 0, 0, 0); }