From 234eb53ed909ac95b748bf62a9fea30702fce8dc Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 14 Aug 2025 18:49:43 +0200 Subject: [PATCH] nb/intel/sandybridge/raminit: Speed up reading SPD EEPROMs Use i2c_eeprom_read() to speed up reading the SPD EEPROMs. TEST=Booted on Lenovo X220 and used cbmem -t: Before: 940:waiting for ME acknowledgment of raminit 116,514 (62,804) After: 940:waiting for ME acknowledgment of raminit 110,212 (57,612) Boots 5msec faster when MRC cache is present. Change-Id: I500d7ff7a66b08b5036c0031e4fa20746d06df19 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/88795 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/sandybridge/raminit.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 9ec8fb6f6e..cd6d173046 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -143,11 +143,16 @@ static void read_spd(spd_ddr3_raw_data *spd, u8 addr, bool id_only) { int j; if (id_only) { - for (j = SPD_DDR3_MOD_ID1; j < 128; j++) - (*spd)[j] = smbus_read_byte(addr, j); + u8 *dest = &(*spd)[SPD_DDR3_MOD_ID1]; + if (i2c_eeprom_read(addr, SPD_DDR3_MOD_ID1, 128 - SPD_DDR3_MOD_ID1, dest) < 0) { + for (j = SPD_DDR3_MOD_ID1; j < 128; j++) + (*spd)[j] = smbus_read_byte(addr, j); + } } else { - for (j = 0; j < SPD_SIZE_MAX_DDR3; j++) - (*spd)[j] = smbus_read_byte(addr, j); + if (i2c_eeprom_read(addr, 0, SPD_SIZE_MAX_DDR3, *spd) < 0) { + for (j = 0; j < SPD_SIZE_MAX_DDR3; j++) + (*spd)[j] = smbus_read_byte(addr, j); + } } }