UPSTREAM: spi: Get rid of SPI_ATOMIC_SEQUENCING

SPI_ATOMIC_SEQUENCING was added to accomodate spi flash controllers with
the ability to perform tx and rx of flash command and response at the
same time. Instead of introducing this notion at SPI flash driver layer,
clean up the interface to SPI used by flash.

Flash uses a command-response kind of communication. Thus, even though
SPI is duplex, flash command needs to be sent out on SPI bus and then
flash response should be received on the bus. Some specialized x86
flash controllers are capable of handling command and response in a
single transaction.

In order to support all the varied cases:
1. Add spi_xfer_vector that takes as input a vector of SPI operations
and calls back into SPI controller driver to process these operations.
2. In order to accomodate flash command-response model, use two vectors
while calling into spi_xfer_vector -- one with dout set to
non-NULL(command) and other with din set to non-NULL(response).
3. For specialized SPI flash controllers combine two successive vectors
if the transactions look like a command-response pair.
4. Provide helper functions for common cases like supporting only 2
vectors at a time, supporting n vectors at a time, default vector
operation to cycle through all SPI op vectors one by one.

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully

Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17681
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I4c9e78c585ad95c40c0d5af078ff8251da286236
Reviewed-on: https://chromium-review.googlesource.com/424871
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/broadcom/cygnus/spi.c

@@ -279,6 +279,7 @@ static const struct spi_ctrlr spi_ctrlr = {
 	.claim_bus = spi_ctrlr_claim_bus,
 	.release_bus = spi_ctrlr_release_bus,
 	.xfer = spi_ctrlr_xfer,
+	.xfer_vector = spi_xfer_two_vectors,
 };
 
 int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave)

src/soc/imgtec/pistachio/Kconfig

@@ -22,7 +22,6 @@ config CPU_IMGTEC_PISTACHIO
 	select GENERIC_UDELAY
 	select HAVE_MONOTONIC_TIMER
 	select HAVE_UART_SPECIAL
-	select SPI_ATOMIC_SEQUENCING
 	select GENERIC_GPIO_LIB
 	select HAVE_HARD_RESET
 	select UART_OVERRIDE_REFCLK

src/soc/imgtec/pistachio/spi.c

@@ -22,10 +22,6 @@
 #include <string.h>
 #include <timer.h>
 
-#if !CONFIG_SPI_ATOMIC_SEQUENCING
-#error "Unsupported SPI driver API"
-#endif
-
 /* Imgtec controller uses 16 bit packet length. */
 #define IMGTEC_SPI_MAX_TRANSFER_SIZE   ((1 << 16) - 1)
 
@@ -496,7 +492,7 @@ static int do_spi_xfer(const struct spi_slave *slave, const void *dout,
 }
 
 static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
-			      size_t bytesout, void *din, size_t bytesin)
+			  size_t bytesout, void *din, size_t bytesin)
 {
 	unsigned int in_sz, out_sz;
 	int ret;
@@ -541,6 +537,7 @@ static const struct spi_ctrlr spi_ctrlr = {
 	.claim_bus = spi_ctrlr_claim_bus,
 	.release_bus = spi_ctrlr_release_bus,
 	.xfer = spi_ctrlr_xfer,
+	.xfer_vector = spi_xfer_two_vectors,
 };
 
 /* Set up communications parameters for a SPI slave. */

src/soc/intel/baytrail/spi.c

@@ -612,6 +612,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
 
 static const struct spi_ctrlr spi_ctrlr = {
 	.xfer = spi_ctrlr_xfer,
+	.xfer_vector = spi_xfer_two_vectors,
 };
 
 int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave)

src/soc/intel/braswell/spi.c

@@ -596,6 +596,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
 
 static const struct spi_ctrlr spi_ctrlr = {
 	.xfer = spi_ctrlr_xfer,
+	.xfer_vector = spi_xfer_two_vectors,
 };
 
 int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave)

src/soc/intel/broadwell/spi.c

@@ -646,6 +646,7 @@ int spi_flash_protect(u32 start, u32 size)
 
 static const struct spi_ctrlr spi_ctrlr = {
 	.xfer = spi_ctrlr_xfer,
+	.xfer_vector = spi_xfer_two_vectors,
 };
 
 int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave)

src/soc/intel/fsp_baytrail/spi.c

@@ -592,6 +592,7 @@ spi_xfer_exit:
 
 static const struct spi_ctrlr spi_ctrlr = {
 	.xfer = spi_ctrlr_xfer,
+	.xfer_vector = spi_xfer_two_vectors,
 };
 
 int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave)

src/soc/intel/fsp_broadwell_de/spi.c

@@ -609,6 +609,7 @@ spi_xfer_exit:
 
 static const struct spi_ctrlr spi_ctrlr = {
 	.xfer = spi_ctrlr_xfer,
+	.xfer_vector = spi_xfer_two_vectors,
 };
 
 int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave)

src/soc/mediatek/mt8173/Kconfig

@@ -9,7 +9,6 @@ config SOC_MEDIATEK_MT8173
 	select ARM64_USE_ARM_TRUSTED_FIRMWARE
 	select BOOTBLOCK_CONSOLE
 	select HAVE_UART_SPECIAL
-	select SPI_ATOMIC_SEQUENCING if SPI_FLASH
 	select HAVE_MONOTONIC_TIMER
 	select GENERIC_UDELAY
 	select GENERIC_GPIO_LIB

src/soc/mediatek/mt8173/spi.c

@@ -293,6 +293,7 @@ static const struct spi_ctrlr spi_ctrlr = {
 	.claim_bus = spi_ctrlr_claim_bus,
 	.release_bus = spi_ctrlr_release_bus,
 	.xfer = spi_ctrlr_xfer,
+	.xfer_vector = spi_xfer_two_vectors,
 };
 
 int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave)

src/soc/qualcomm/ipq40xx/Kconfig

@@ -7,7 +7,6 @@ config SOC_QC_IPQ40XX
 	select ARCH_RAMSTAGE_ARMV7
 	select BOOTBLOCK_CONSOLE
 	select HAVE_UART_SPECIAL
-	select SPI_ATOMIC_SEQUENCING
 	select GENERIC_GPIO_LIB
 	select HAVE_MONOTONIC_TIMER
 

src/soc/qualcomm/ipq806x/Kconfig

@@ -7,7 +7,6 @@ config SOC_QC_IPQ806X
 	select ARCH_RAMSTAGE_ARMV7
 	select BOOTBLOCK_CONSOLE
 	select HAVE_UART_SPECIAL
-	select SPI_ATOMIC_SEQUENCING
 	select GENERIC_GPIO_LIB
 
 if SOC_QC_IPQ806X