Rework the Geode delay control setup to table driven and much more readable.
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@435 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Marc Jones
parent
c133c1bf2b
commit
22895ba000
2 changed files with 57 additions and 123 deletions
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@ -247,6 +247,42 @@ u32 pci_speed(void)
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}
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}
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/**
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* Delay Control Settings Table from AMD (MCP 0x4C00000F)
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* =========================================================================
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*/
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const struct delay_controls {
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u8 dimms;
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u8 devices;
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u32 slow_hi;
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u32 slow_low;
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u32 fast_hi;
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u32 fast_low;
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} delay_control_table [] = {
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/* DIMMs Devs Slow (<=333MHz) Fast (>334MHz) */
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{ 1, 4, 0x0837100FF, 0x056960004, 0x0827100FF, 0x056960004 },
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{ 1, 8, 0x0837100AA, 0x056960004, 0x0827100AA, 0x056960004 },
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{ 1, 16, 0x0837100AA, 0x056960004, 0x082710055, 0x056960004 },
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{ 2, 8, 0x0837100A5, 0x056960004, 0x082710000, 0x056960004 },
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{ 2, 16, 0x0937100A5, 0x056960004, 0x0C27100A5, 0x056960004 },
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{ 2, 20, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 },
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{ 2, 24, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 },
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{ 2, 32, 0x0B37100A5, 0x056960004, 0x0B2710000, 0x056960004 },
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};
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/**
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* - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM
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* in slot 0, but it should be clear for all 2 DIMM settings and if a
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* single DIMM is in slot 1. Bits 54:52 should always be set to '111'.
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*
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* Settings for single DIMM and no VTT termination (Like db800 platform)
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* 0xF2F100FF 0x56960004
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* -------------------------------------
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* ADDR/CTL have 22 ohm series R
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* DQ/DQM/DQS have 33 ohm series R
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*/
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/**
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* set_delay_control. This is Black Magic DRAM timing
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* juju(http://www.thefreedictionary.com/juju) Dram delay depends on
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@ -263,12 +299,10 @@ u32 pci_speed(void)
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* @param dimm1 DIMM 1 SMBus address
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* @param sram_width Data width of the SDRAM
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*/
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void set_delay_control(u8 dimm0, u8 dimm1)
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{
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u32 msrnum, glspeed;
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u8 spdbyte0, spdbyte1;
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int numdimms = 0;
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u8 spdbyte0, spdbyte1, dimms, i;
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struct msr msr;
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glspeed = geode_link_speed();
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@ -315,9 +349,10 @@ void set_delay_control(u8 dimm0, u8 dimm1)
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* # of Devices = Module Width (SPD6) / Device Width(SPD13) * Physical Banks(SPD5)
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* Note - We only support module width of 64.
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*/
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dimms = 0;
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spdbyte0 = smbus_read_byte(dimm0, SPD_PRIMARY_SDRAM_WIDTH);
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if (spdbyte0 != 0xFF) {
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numdimms++;
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dimms++;
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spdbyte0 = (unsigned char)64 / spdbyte0 *
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(unsigned char)(smbus_read_byte(dimm0, SPD_NUM_DIMM_BANKS));
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} else {
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@ -326,134 +361,32 @@ void set_delay_control(u8 dimm0, u8 dimm1)
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spdbyte1 = smbus_read_byte(dimm1, SPD_PRIMARY_SDRAM_WIDTH);
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if (spdbyte1 != 0xFF) {
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numdimms++;
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dimms++;
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spdbyte1 = (unsigned char)64 / spdbyte1 *
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(unsigned char)(smbus_read_byte(dimm1, SPD_NUM_DIMM_BANKS));
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} else {
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spdbyte1 = 0;
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}
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/* The current thinking. Subject to change...
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; "FUTURE ROBUSTNESS" PROPOSAL
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; ----------------------------
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; DIMM Max MBUS MC 0x2000001A bits 26:24
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;DIMMs devices Frequency MCP 0x4C00000F Setting vvv
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;----- ------- --------- ---------------------- ----------
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;1 4 400MHz 0x82*100FF 0x56960004 4
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;1 8 400MHz 0x82*100AA 0x56960004 4
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;1 16 400MHz 0x82*10055 0x56960004 4
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;
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;2 4,4 400MHz 0x82710000 0x56960004 4
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;2 8,8 400MHz 0xC27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE ***
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;
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;2 16,4 >333 0xB27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE ***
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;2 16,8 >333 0xB27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE ***
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;2 16,16 >333 0xB2710000 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE ***
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;
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;1 4 <=333MHz 0x83*100FF 0x56960004 3
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;1 8 <=333MHz 0x83*100AA 0x56960004 3
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;1 16 <=333MHz 0x83*100AA 0x56960004 3
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;
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;2 4,4 <=333MHz 0x837100A5 0x56960004 3
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;2 8,8 <=333MHz 0x937100A5 0x56960004 3
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;
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;2 16,4 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE ***
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;2 16,8 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE ***
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;2 16,16 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE ***
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;=========================================================================
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;* - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM in slot 0,
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; but it should be clear for all 2 DIMM settings and if a single DIMM is in slot 1.
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; Bits 54:52 should always be set to '111'.
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;No VTT termination
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;-------------------------------------
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;ADDR/CTL have 22 ohm series R
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;DQ/DQM/DQS have 33 ohm series R
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;
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; DIMM Max MBUS
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;DIMMs devices Frequency MCP 0x4C00000F Setting
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;----- ------- --------- ----------------------
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;1 4 400MHz 0xF2F100FF 0x56960004 4 The MC changes improve Salsa.
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;1 8 400MHz 0xF2F100FF 0x56960004 4 Delay controls no real change,
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;1 4 <=333MHz 0xF2F100FF 0x56960004 3 just fixing typo in left side.
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;1 8 <=333MHz 0xF2F100FF 0x56960004 3
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;1 16 <=333MHz 0xF2F100FF 0x56960004 3
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*/
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/* zero GLCP_DELAY_CONTROLS MSR */
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msr.hi = msr.lo = 0;
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if (spdbyte0 == 0 || spdbyte1 == 0) {
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/* one dimm solution */
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if (spdbyte1 == 0) {
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msr.hi |= 0x000800000;
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}
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spdbyte0 += spdbyte1;
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if (spdbyte0 > 8) {
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/* large dimm */
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/* save some power, disable clock to second DIMM if it is empty */
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if (spdbyte1 == 0) {
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msr.hi |= DELAY_UPPER_DISABLE_CLK135;
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}
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spdbyte0 += spdbyte1;
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for (i = 0; i < ARRAY_SIZE(delay_control_table); i++) {
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if ((dimms == delay_control_table[i].dimms) &&
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(spdbyte0 <= delay_control_table[i].devices)) {
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if (glspeed < 334) {
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msr.hi |= 0x0837100AA;
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msr.lo |= 0x056960004;
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msr.hi |= delay_control_table[i].slow_hi;
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msr.lo |= delay_control_table[i].slow_low;
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} else {
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msr.hi |= 0x082710055;
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msr.lo |= 0x056960004;
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}
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} else if (spdbyte0 > 4) {
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/* medium dimm */
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if (glspeed < 334) {
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msr.hi |= 0x0837100AA;
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msr.lo |= 0x056960004;
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} else {
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msr.hi |= 0x0827100AA;
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msr.lo |= 0x056960004;
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}
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} else {
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/* small dimm */
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if (glspeed < 334) {
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msr.hi |= 0x0837100FF;
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msr.lo |= 0x056960004;
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} else {
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msr.hi |= 0x0827100FF;
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msr.lo |= 0x056960004;
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}
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}
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} else {
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/* two dimm solution */
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spdbyte0 += spdbyte1;
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if (spdbyte0 > 24) {
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/* huge dimms */
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if (glspeed < 334) {
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msr.hi |= 0x0B37100A5;
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msr.lo |= 0x056960004;
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} else {
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msr.hi |= 0x0B2710000;
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msr.lo |= 0x056960004;
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}
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} else if (spdbyte0 > 16) {
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/* large dimms */
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if (glspeed < 334) {
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msr.hi |= 0x0B37100A5;
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msr.lo |= 0x056960004;
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} else {
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msr.hi |= 0x0B27100A5;
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msr.lo |= 0x056960004;
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}
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} else if (spdbyte0 >= 8) {
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/* medium dimms */
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if (glspeed < 334) {
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msr.hi |= 0x0937100A5;
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msr.lo |= 0x056960004;
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} else {
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msr.hi |= 0x0C27100A5;
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msr.lo |= 0x056960004;
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}
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} else {
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/* small dimms */
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if (glspeed < 334) {
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msr.hi |= 0x0837100A5;
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msr.lo |= 0x056960004;
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} else {
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msr.hi |= 0x082710000;
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msr.lo |= 0x056960004;
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msr.hi |= delay_control_table[i].fast_hi;
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msr.lo |= delay_control_table[i].fast_low;
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}
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}
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}
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@ -354,7 +354,8 @@
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#define GLCP_GLD_MSR_ERROR (MSR_GLCP + 0x2003)
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#define GLCP_GLD_MSR_PM (MSR_GLCP + 0x2004)
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#define GLCP_DELAY_CONTROLS (MSR_GLCP + 0x0F)
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#define DELAY_LOWER_STATUS_MASK 0x7C0
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#define DELAY_UPPER_DISABLE_CLK135 (1 << 23)
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#define DELAY_LOWER_STATUS_MASK 0x7C0
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#define GLCP_SYS_RSTPLL (MSR_GLCP + 0x14) /* R/W */
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#define RSTPLL_UPPER_GLMULT_SHIFT 7
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#define RSTPLL_UPPER_GLMULT_MASK 0x1F
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