Start of merge from work on the AMD760MP platform.

This is the safe part just additions to files, and comment changes

src/sdram/generic_dump_spd.inc

@@ -0,0 +1,38 @@
+dump_spd_registers:
+	movl $((0 << 8) | SMBUS_MEM_DEVICE_START), %ebx
+dump_spd_reg_dimm:
+	TTYS0_TX_CHAR($'\r')
+	TTYS0_TX_CHAR($'\n')
+	TTYS0_TX_CHAR($'d')
+	TTYS0_TX_CHAR($'i')
+	TTYS0_TX_CHAR($'m')
+	TTYS0_TX_CHAR($'m')
+	TTYS0_TX_CHAR($' ')
+	movb %bl, %al
+	CALLSP(ttys0_tx_hex8)	
+	TTYS0_TX_CHAR($'\r')
+	TTYS0_TX_CHAR($'\n')
+dump_spd_reg_byte:
+	CALLSP(smbus_read_byte)
+	jz dump_spd_reg_next_dimm
+
+	CALLSP(ttys0_tx_hex8)
+	TTYS0_TX_CHAR($' ')
+	incb %bh
+	testb $0x0F, %bh
+	jnz dump_spd_reg_next_byte
+	TTYS0_TX_CHAR($'\r')
+	TTYS0_TX_CHAR($'\n')
+
+dump_spd_reg_next_byte:
+	cmpb $0, %bh
+	jne dump_spd_reg_byte
+
+dump_spd_reg_next_dimm:
+	TTYS0_TX_CHAR($'\r')
+	TTYS0_TX_CHAR($'\n')
+	xorb %bh, %bh
+	add $SMBUS_MEM_DEVICE_INC, %bl
+	cmpb $(SMBUS_MEM_DEVICE_END + SMBUS_MEM_DEVICE_INC), %bl
+	jne dump_spd_reg_dimm
+dump_spd_registers_out:

src/sdram/generic_sdram_enable.inc

@@ -0,0 +1,73 @@
+jmp generic_sdram_enable_out
+
+ram_enable_1:	.string "Ram Enable 1\r\n"
+ram_enable_2:	.string "Ram Enable 2\r\n"
+ram_enable_3:	.string "Ram Enable 3\r\n"
+ram_enable_4:	.string "Ram Enable 4\r\n"
+ram_enable_5:	.string "Ram Enable 5\r\n"
+
+	/* Estimate that SLOW_DOWN_IO takes about 50&76us*/
+	/* delay for 200us */
+
+#define DO_DELAY \
+	movl $4, %edi		; \
+1:	SLOW_DOWN_IO		; \
+	decl %edi		; \
+	jnz 1b
+		
+
+enable_sdram:
+/*	now the fun begins.
+	turn on the dram and wait a while (this from the intel book)
+	turn power on and set the nop bit too
+ */
+	TTYS0_TX_STRING($ram_enable_1)
+	/* SDRAMC */
+	SET_RAM_COMMAND(RAM_COMMAND_NOP)
+
+	DO_DELAY
+
+	ASSERT_RAM_COMMAND() /* nop command */
+
+	/* Precharge all */
+	SET_RAM_COMMAND(RAM_COMMAND_PRECHARGE)
+	ASSERT_RAM_COMMAND()
+	
+	/* wait until the all banks idle state... */
+
+	TTYS0_TX_STRING($ram_enable_2)
+
+	/* Now we need 8 AUTO REFRESH / CBR cycles to be performed */
+
+	SET_RAM_COMMAND(RAM_COMMAND_CBR)
+	ASSERT_RAM_COMMAND()
+	ASSERT_RAM_COMMAND()
+	ASSERT_RAM_COMMAND()
+	ASSERT_RAM_COMMAND()
+	ASSERT_RAM_COMMAND()
+	ASSERT_RAM_COMMAND()
+	ASSERT_RAM_COMMAND()
+	ASSERT_RAM_COMMAND()
+
+	TTYS0_TX_STRING($ram_enable_3)
+
+	/* mode register set */
+	SET_RAM_MODE_REGISTER
+	
+	/* MAx[14:0] lines,
+	 * MAx[2:0 ] 010 == burst mode of 4
+	 * MAx[3:3 ] 1 == interleave wrap type
+	 * MAx[4:4 ] == CAS# latency bit
+	 * MAx[6:5 ] == 01
+	 * MAx[12:7] ==	0
+	 */
+
+	TTYS0_TX_STRING($ram_enable_4)
+
+	/* normal operation */
+	SET_RAM_COMMAND(RAM_COMMAND_NONE)
+
+	TTYS0_TX_STRING($ram_enable_5)
+	RET_LABEL(enable_sdram)
+
+generic_sdram_enable_out:

src/sdram/generic_zero_ecc_sdram.inc

@@ -0,0 +1,102 @@
+jmp	ecc_ram_initialize
+
+ecc_ram_1:		.string "ecc_ram_1\r\n"
+ecc_ram_2:		.string "ecc_ram_2\r\n"
+ecc_ram_3:		.string "ecc_ram_3\r\n"
+ecc_ram_4:		.string "ecc_ram_4\r\n"
+
+ecc_ram_initialize:
+	TTYS0_TX_STRING($ecc_ram_1)
+	CALL_LABEL(get_ecc_ram_size_bytes_ebx)
+
+	/* If we don't have an ECC SDRAM size skip the zeroing */
+	testl	%ebx, %ebx
+	jz	zero_ecc_ram_out
+	movl	%ebx, %ebp
+
+	/* Compute the next greater power of two memory size, to use in the mtrrs */
+	bsrl	%ebp, %ecx
+	movl	$1, %esi
+	shll	%cl, %esi
+	/* See if I need to round up */
+	subl	$1, %esi
+	testl	%esi, %ebp
+	jz	1f
+	incl	%ecx
+1:	movl	$1, %esi
+	shll	%cl, %esi
+
+	/* Set caching on all of memory into write-combining mode. 
+	 * So we can zero it quickly.
+	 */
+	/* Disable the cache while we set up a new MTRR over memory */
+	movl	%cr0, %eax
+	orl	$0x40000000, %eax
+	movl	%eax, %cr0
+
+	movl	$0x200, %ecx		/* mtrr[0] physical base register */
+	movl	$0x00000000, %edx
+	movl	$0x00000001, %eax
+	wrmsr
+
+	movl	$0x201, %ecx		/* mtrr[0] physical mask register */
+	movl	$0x0000000f, %edx
+	xorl	%eax, %eax
+	subl	%esi, %eax
+	andl	$0xfffff000, %eax
+	orl	$0x800, %eax
+	wrmsr
+
+	/* Reenable the cache now that the mtrr is set up */
+	movl	%cr0, %eax
+	andl	$0x9fffffff, %eax
+	movl	%eax, %cr0
+
+	/* Now zero the memory */
+	TTYS0_TX_STRING($ecc_ram_2)
+	cld
+
+#if !defined(HAVE_PC80_MEMORY_HOLE)
+	/* The 640KB - 1MB memory should not be enabled at this point. */
+	xorl	%eax, %eax
+	xorl	%edi, %edi
+	movl	%ebp, %ecx
+	shrl	$2, %ecx
+	rep	stosl
+
+#else /* HAVE_PC80_MEMORY_HOLE */
+
+	xorl	%eax, %eax		/* zero */
+	xorl	%edi, %edi		/* destination */
+	movl	$0x28000,%ecx
+	rep	stosl
+
+	xorl	%eax, %eax
+	movl	$0x100000, %edi
+	movl	%ebp, %ecx
+	subl	%edi, %ecx
+	shrl	$2, %ecx
+	rep	stosl
+#endif /* HAVE_PC80_MEMORY_HOLE */
+
+	TTYS0_TX_STRING($ecc_ram_3)
+
+	/* Change caching on memory from write-combining to write-back. */
+	/* Disable the cache while we set up a new MTRR over memory */
+	movl	%cr0, %eax
+	orl	$0x40000000, %eax
+	movl	%eax, %cr0
+
+	movl	$0x200, %ecx
+	movl	$0x00000000, %edx
+	movl	$0x00000006, %eax
+	wrmsr
+
+	/* Reenable the cache now that the mtrr is set up */
+	movl	%cr0, %eax
+	andl	$0x9fffffff, %eax
+	movl	%eax, %cr0
+
+zero_ecc_ram_out:
+	TTYS0_TX_STRING($ecc_ram_4)
+

src/sdram/smbus_pcibus.inc

@@ -1,5 +1,5 @@
 /* Useful macros PCIBUS, and SMBUS functions for getting DRAM going. */
-/* courtesy Eric Beiderman of linuxnetworx.com */
+/* courtesy Eric Biederman of linuxnetworx.com */
 
 #define CS_WRITE_BYTE(addr, byte) \
 	movl $addr, %eax	; \