Start of merge from work on the AMD760MP platform.
This is the safe part just additions to files, and comment changes
This commit is contained in:
Eric W. Biederman
parent
ad44ad6bc8
commit
228148aa23
63 changed files with 6591 additions and 3 deletions
44
src/pc80/i8259.c
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44
src/pc80/i8259.c
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#ifdef I8259
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#include <pc80/i8259.h>
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#include <arch/io.h>
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/* code taken from:
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!
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! setup.S Copyright (C) 1991, 1992 Linus Torvalds
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!
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! setup.s is responsible for getting the system data from the BIOS,
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! and putting them into the appropriate places in system memory.
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! both setup.s and system has been loaded by the bootblock.
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*/
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/* we're getting screwed again and again by this problem of the 8259.
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* so we're going to leave this lying around for inclusion into
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* crt0.S on an as-needed basis.
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! well, that went ok, I hope. Now we have to reprogram the interrupts :-(
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! we put them right after the intel-reserved hardware interrupts, at
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! int 0x20-0x2F. There they won't mess up anything. Sadly IBM really
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! messed this up with the original PC, and they haven't been able to
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! rectify it afterwards. Thus the bios puts interrupts at 0x08-0x0f,
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! which is used for the internal hardware interrupts as well. We just
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! have to reprogram the 8259's, and it isn't fun.
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*/
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void setup_i8259(void)
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{
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outb(0x11, 0x20); /*! initialization sequence to 8259A-1*/
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outb(0x11, 0xA0); /*! and to 8259A-2*/
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outb(0x20, 0x21); /*! start of hardware int's (0x20)*/
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outb(0x28, 0xA1); /*! start of hardware int's 2 (0x28)*/
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outb(0x04, 0x21); /*! 8259-1 is master*/
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outb(0x02, 0xA1); /*! 8259-2 is slave*/
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outb(0x01, 0x21); /*! 8086 mode for both*/
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outb(0x01, 0xA1);
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outb(0xFF, 0xA1); /*! mask off all interrupts for now*/
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outb(0xFB, 0x21); /*! mask all irq's but irq2 which is cascaded*/
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}
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/*
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* I like the way Linus says it:
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! Well, that certainly wasn't fun :-(. Hopefully it works, and we don't
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! need no steenking BIOS anyway (except for the initial loading :-).
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*/
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#endif /* I8259 */
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43
src/pc80/isa-dma.c
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43
src/pc80/isa-dma.c
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@ -0,0 +1,43 @@
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#include <arch/io.h>
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/* DMA controller registers */
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#define DMA1_CMD_REG 0x08 /* command register (w) */
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#define DMA1_STAT_REG 0x08 /* status register (r) */
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#define DMA1_REQ_REG 0x09 /* request register (w) */
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#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
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#define DMA1_MODE_REG 0x0B /* mode register (w) */
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#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
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#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
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#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
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#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
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#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
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#define DMA2_CMD_REG 0xD0 /* command register (w) */
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#define DMA2_STAT_REG 0xD0 /* status register (r) */
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#define DMA2_REQ_REG 0xD2 /* request register (w) */
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#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
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#define DMA2_MODE_REG 0xD6 /* mode register (w) */
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#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
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#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
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#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
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#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
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#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
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#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
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#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
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#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
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#define DMA_AUTOINIT 0x10
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void isa_dma_init(void)
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{
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/* slave at 0x00 - 0x0f */
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/* master at 0xc0 - 0xdf */
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/* 0x80 - 0x8f DMA page registers */
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/* DMA: 0x00, 0x02, 0x4, 0x06 base address for DMA channel */
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outb(0, DMA1_RESET_REG);
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outb(0, DMA2_RESET_REG);
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outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
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outb(0, DMA2_MASK_REG);
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}
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@ -2,7 +2,7 @@
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static char rcsid[] = "$Id$";
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#endif
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#include <cpu/p5/io.h>
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#include <arch/io.h>
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#include <subr.h>
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/* much better keyboard init courtesy ollie@sis.com.tw
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TODO: Typematic Setting, the keyboard is too slow for me */
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@ -13,7 +13,7 @@ void pc_keyboard_init()
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/* send cmd = 0xAA, self test 8042 */
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outb(0xaa, 0x64);
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/* empty inut bufferm or any other command/data will be lost */
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/* empty input buffer or any other command/data will be lost */
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while ((inb(0x64) & 0x02))
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post_code(0);
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/* empty output buffer or any other command/data will be lost */
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@ -52,3 +52,4 @@ void pc_keyboard_init()
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if ((regval = inb(0x60) != 0xaa))
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return;
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}
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161
src/pc80/mc146818rtc.c
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src/pc80/mc146818rtc.c
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@ -0,0 +1,161 @@
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#include <arch/io.h>
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#include <printk.h>
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#define RTC_PORT(x) (0x70 + (x))
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#define CMOS_READ(addr) ({ \
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outb_p((addr),RTC_PORT(0)); \
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inb_p(RTC_PORT(1)); \
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})
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#define CMOS_WRITE(val, addr) ({ \
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outb_p((addr),RTC_PORT(0)); \
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outb_p((val),RTC_PORT(1)); \
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})
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/* control registers - Moto names
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*/
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#define RTC_REG_A 10
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#define RTC_REG_B 11
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#define RTC_REG_C 12
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#define RTC_REG_D 13
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/**********************************************************************
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* register details
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**********************************************************************/
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#define RTC_FREQ_SELECT RTC_REG_A
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/* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus,
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* reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
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* totalling to a max high interval of 2.228 ms.
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*/
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# define RTC_UIP 0x80
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# define RTC_DIV_CTL 0x70
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/* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
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# define RTC_REF_CLCK_4MHZ 0x00
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# define RTC_REF_CLCK_1MHZ 0x10
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# define RTC_REF_CLCK_32KHZ 0x20
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/* 2 values for divider stage reset, others for "testing purposes only" */
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# define RTC_DIV_RESET1 0x60
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# define RTC_DIV_RESET2 0x70
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/* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
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# define RTC_RATE_SELECT 0x0F
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# define RTC_RATE_NONE 0x00
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# define RTC_RATE_32786HZ 0x01
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# define RTC_RATE_16384HZ 0x02
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# define RTC_RATE_8192HZ 0x03
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# define RTC_RATE_4096HZ 0x04
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# define RTC_RATE_2048HZ 0x05
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# define RTC_RATE_1024HZ 0x06
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# define RTC_RATE_512HZ 0x07
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# define RTC_RATE_256HZ 0x08
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# define RTC_RATE_128HZ 0x09
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# define RTC_RATE_64HZ 0x0a
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# define RTC_RATE_32HZ 0x0b
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# define RTC_RATE_16HZ 0x0c
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# define RTC_RATE_8HZ 0x0d
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# define RTC_RATE_4HZ 0x0e
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# define RTC_RATE_2HZ 0x0f
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/**********************************************************************/
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#define RTC_CONTROL RTC_REG_B
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# define RTC_SET 0x80 /* disable updates for clock setting */
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# define RTC_PIE 0x40 /* periodic interrupt enable */
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# define RTC_AIE 0x20 /* alarm interrupt enable */
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# define RTC_UIE 0x10 /* update-finished interrupt enable */
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# define RTC_SQWE 0x08 /* enable square-wave output */
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# define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
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# define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
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# define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */
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/**********************************************************************/
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#define RTC_INTR_FLAGS RTC_REG_C
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/* caution - cleared by read */
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# define RTC_IRQF 0x80 /* any of the following 3 is active */
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# define RTC_PF 0x40
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# define RTC_AF 0x20
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# define RTC_UF 0x10
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/**********************************************************************/
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#define RTC_VALID RTC_REG_D
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# define RTC_VRT 0x80 /* valid RAM and time */
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/**********************************************************************/
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/* On PCs, the checksum is built only over bytes 16..45 */
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#define PC_CKS_RANGE_START 16
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#define PC_CKS_RANGE_END 45
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#define PC_CKS_LOC 46
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static int rtc_checksum_valid(void)
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{
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int i;
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unsigned sum, old_sum;
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sum = 0;
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for(i = PC_CKS_RANGE_START; i <= PC_CKS_RANGE_END; i++) {
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sum += CMOS_READ(i);
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}
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sum &= 0xffff;
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old_sum = (CMOS_READ(PC_CKS_LOC) << 8) | CMOS_READ(PC_CKS_LOC+1);
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return sum == old_sum;
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}
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static void rtc_set_checksum(void)
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{
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int i;
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unsigned sum;
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sum = 0;
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for(i = PC_CKS_RANGE_START; i <= PC_CKS_RANGE_END; i++) {
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sum += CMOS_READ(i);
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}
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sum &= 0xffff;
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CMOS_WRITE(((sum >> 8) & 0xff), PC_CKS_LOC);
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CMOS_WRITE(((sum >> 0) & 0xff), PC_CKS_LOC+1);
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}
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#define RTC_CONTROL_DEFAULT (RTC_24H)
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#define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ)
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#if 0 /* alpha setup */
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#undef RTC_CONTROL_DEFAULT
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#undef RTC_FREQ_SELECT_DEFAULT
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#define RTC_CONTROL_DEFAULT (RTC_SQWE | RTC_24H)
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#define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ)
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#endif
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void rtc_init(void)
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{
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unsigned char x;
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int cmos_valid;
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/* See if there has been a CMOS power problem. */
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x = CMOS_READ(RTC_VALID);
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cmos_valid = !(x & RTC_VRT);
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/* See if there is a CMOS checksum error */
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cmos_valid = rtc_checksum_valid();
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if (!cmos_valid) {
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int i;
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printk_warning("RTC power problem, zeroing cmos\n");
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for(i = 0x0; i < 128; i++) {
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CMOS_WRITE(0, i);
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}
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/* Now setup a default date of Sat 1 January 2000 */
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CMOS_WRITE(0, 0x00); /* seconds */
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CMOS_WRITE(0, 0x02); /* minutes */
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CMOS_WRITE(1, 0x04); /* hours */
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CMOS_WRITE(7, 0x06); /* day of week */
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CMOS_WRITE(1, 0x07); /* day of month */
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CMOS_WRITE(1, 0x08); /* month */
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CMOS_WRITE(0, 0x09); /* year */
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}
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/* Setup the real time clock */
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CMOS_WRITE(RTC_CONTROL_DEFAULT, RTC_CONTROL);
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/* Setup the frequency it operates at */
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CMOS_WRITE(RTC_FREQ_SELECT_DEFAULT, RTC_FREQ_SELECT);
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/* Make certain we have a valid checksum */
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rtc_set_checksum();
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/* Clear any pending interrupts */
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(void) CMOS_READ(RTC_INTR_FLAGS);
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}
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