From 2207a4b59ae120348f60328b085a0a006646e58c Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Tue, 10 Jun 2025 14:03:37 -0700 Subject: [PATCH] vc/intel/fsp/fsp2_0/pantherlake: Add TDC current limit configuration This commit exposes the Thermal Design Current (TDC) limit in the FSP_M_CONFIG structure. The TDC Current Limit is defined in 1/8A increments. This allows for more precise control over the thermal design current settings, enhancing power management capabilities. Change-Id: Ie35611d5cdc14114542ac1a61611aa333c4bb1c9 Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/88037 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Zhixing Ma --- .../intel/fsp/fsp2_0/pantherlake/FspmUpd.h | 63 ++++++++++--------- 1 file changed, 33 insertions(+), 30 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h index c5b16d6dce..2e420cbec8 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h @@ -2323,9 +2323,12 @@ typedef struct { **/ UINT16 PsysPmax; -/** Offset 0x0872 - Reserved +/** Offset 0x0872 - Thermal Design Current current limit + TDC Current Limit, defined in 1/8A increments. Range 0-32767. For a TDC Current + Limit of 125A, enter 1000. 0 = 0 Amps. 0: Auto. [0] for IA, [1] for GT, + [2] for SA, [3] for atom, [4]-[5] are Reserved. **/ - UINT8 Reserved66[12]; + UINT16 TdcCurrentLimit[6]; /** Offset 0x087E - AcLoadline AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 @@ -2343,7 +2346,7 @@ typedef struct { /** Offset 0x0896 - Reserved **/ - UINT8 Reserved67[116]; + UINT8 Reserved66[116]; /** Offset 0x090A - Thermal Design Current enable/disable Thermal Design Current enable/disable; 0: Disable; 1: Enable. [0] for IA, @@ -2353,7 +2356,7 @@ typedef struct { /** Offset 0x0910 - Reserved **/ - UINT8 Reserved68[6]; + UINT8 Reserved67[6]; /** Offset 0x0916 - Disable Fast Slew Rate for Deep Package C States for VR domains This option needs to be configured to reduce acoustic noise during deeper C states. @@ -2375,7 +2378,7 @@ typedef struct { /** Offset 0x0922 - Reserved **/ - UINT8 Reserved69[6]; + UINT8 Reserved68[6]; /** Offset 0x0928 - Thermal Design Current time window Auto = 0 is default. Range is from 1ms to 448s. 0: Auto. [0] for IA, [1] @@ -2385,7 +2388,7 @@ typedef struct { /** Offset 0x0940 - Reserved **/ - UINT8 Reserved70[8]; + UINT8 Reserved69[8]; /** Offset 0x0948 - DLVR RFI Enable Enable/Disable DLVR RFI frequency hopping. 0: Disable; 1: Enable. @@ -2395,7 +2398,7 @@ typedef struct { /** Offset 0x0949 - Reserved **/ - UINT8 Reserved71[13]; + UINT8 Reserved70[13]; /** Offset 0x0956 - VR Fast Vmode ICC Limit support Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds @@ -2420,7 +2423,7 @@ typedef struct { /** Offset 0x096E - Reserved **/ - UINT8 Reserved72[28]; + UINT8 Reserved71[28]; /** Offset 0x098A - PCH Port80 Route Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. @@ -2437,7 +2440,7 @@ typedef struct { /** Offset 0x098C - Reserved **/ - UINT8 Reserved73[4]; + UINT8 Reserved72[4]; /** Offset 0x0990 - PMR Size Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot @@ -2463,7 +2466,7 @@ typedef struct { /** Offset 0x0997 - Reserved **/ - UINT8 Reserved74; + UINT8 Reserved73; /** Offset 0x0998 - Base addresses for VT-d function MMIO access Base addresses for VT-d MMIO access per VT-d engine @@ -2472,7 +2475,7 @@ typedef struct { /** Offset 0x09BC - Reserved **/ - UINT8 Reserved75[20]; + UINT8 Reserved74[20]; /** Offset 0x09D0 - MMIO Size Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB @@ -2487,7 +2490,7 @@ typedef struct { /** Offset 0x09D4 - Reserved **/ - UINT8 Reserved76[36]; + UINT8 Reserved75[36]; /** Offset 0x09F8 - Enable above 4GB MMIO resource support Enable/disable above 4GB MMIO resource support @@ -2503,7 +2506,7 @@ typedef struct { /** Offset 0x09FA - Reserved **/ - UINT8 Reserved77[10]; + UINT8 Reserved76[10]; /** Offset 0x0A04 - Enable/Disable CrashLog Device Enable or Disable CrashLog/Telemetry Device 0- Disable, 1- Enable @@ -2513,7 +2516,7 @@ typedef struct { /** Offset 0x0A08 - Reserved **/ - UINT8 Reserved78[20]; + UINT8 Reserved77[20]; /** Offset 0x0A1C - Platform Debug Option Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n @@ -2530,7 +2533,7 @@ typedef struct { /** Offset 0x0A1D - Reserved **/ - UINT8 Reserved79[14]; + UINT8 Reserved78[14]; /** Offset 0x0A2B - Program GPIOs for LFP on DDI port-A device 0=Disabled,1(Default)=eDP, 2=MIPI DSI @@ -2540,7 +2543,7 @@ typedef struct { /** Offset 0x0A2C - Reserved **/ - UINT8 Reserved80[2]; + UINT8 Reserved79[2]; /** Offset 0x0A2E - Program GPIOs for LFP on DDI port-B device 0(Default)=Disabled,1=eDP, 2=MIPI DSI @@ -2634,7 +2637,7 @@ typedef struct { /** Offset 0x0A3D - Reserved **/ - UINT8 Reserved81[3]; + UINT8 Reserved80[3]; /** Offset 0x0A40 - Temporary MMIO address for GMADR The reference code will use this as Temporary MMIO address space to access GMADR @@ -2653,7 +2656,7 @@ typedef struct { /** Offset 0x0A50 - Reserved **/ - UINT8 Reserved82[2]; + UINT8 Reserved81[2]; /** Offset 0x0A52 - Enable/Disable Memory Bandwidth Compression 0=Disable, 1(Default)=Enable @@ -2683,7 +2686,7 @@ typedef struct { /** Offset 0x0A56 - Reserved **/ - UINT8 Reserved83[2]; + UINT8 Reserved82[2]; /** Offset 0x0A58 - Intel Graphics VBT (Video BIOS Table) Size Size of Internal Graphics VBT Image @@ -2692,7 +2695,7 @@ typedef struct { /** Offset 0x0A5C - Reserved **/ - UINT8 Reserved84[4]; + UINT8 Reserved83[4]; /** Offset 0x0A60 - Graphics Configuration Ptr Points to VBT @@ -2720,7 +2723,7 @@ typedef struct { /** Offset 0x0A72 - Reserved **/ - UINT8 Reserved85[16]; + UINT8 Reserved84[16]; /** Offset 0x0A82 - TCSS USB HOST (xHCI) Enable Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below @@ -2730,7 +2733,7 @@ typedef struct { /** Offset 0x0A83 - Reserved **/ - UINT8 Reserved86[4]; + UINT8 Reserved85[4]; /** Offset 0x0A87 - TCSS Type C Port 0 Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE, @@ -2762,7 +2765,7 @@ typedef struct { /** Offset 0x0A8B - Reserved **/ - UINT8 Reserved87; + UINT8 Reserved86; /** Offset 0x0A8C - TypeC port GPIO setting GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined @@ -2830,7 +2833,7 @@ typedef struct { /** Offset 0x0AC9 - Reserved **/ - UINT8 Reserved88; + UINT8 Reserved87; /** Offset 0x0ACA - DLL Weak Lock Support Enables/Disable DLL Weak Lock Support @@ -2840,7 +2843,7 @@ typedef struct { /** Offset 0x0ACB - Reserved **/ - UINT8 Reserved89; + UINT8 Reserved88; /** Offset 0x0ACC - Rx DQS Delay Comp Support Enables/Disable Rx DQS Delay Comp Support @@ -2850,7 +2853,7 @@ typedef struct { /** Offset 0x0ACD - Reserved **/ - UINT8 Reserved90[2]; + UINT8 Reserved89[2]; /** Offset 0x0ACF - Mrc Failure On Unsupported Dimm Enables/Disable Mrc Failure On Unsupported Dimm @@ -2860,7 +2863,7 @@ typedef struct { /** Offset 0x0AD0 - Reserved **/ - UINT8 Reserved91[4]; + UINT8 Reserved90[4]; /** Offset 0x0AD4 - DynamicMemoryBoost Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is @@ -2878,7 +2881,7 @@ typedef struct { /** Offset 0x0ADC - Reserved **/ - UINT8 Reserved92[9]; + UINT8 Reserved91[9]; /** Offset 0x0AE5 - Vref Offset Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset @@ -2889,7 +2892,7 @@ typedef struct { /** Offset 0x0AE6 - Reserved **/ - UINT8 Reserved93[2]; + UINT8 Reserved92[2]; /** Offset 0x0AE8 - tRRSG Delta Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT @@ -3005,7 +3008,7 @@ typedef struct { /** Offset 0x0AF8 - Reserved **/ - UINT8 Reserved94[112]; + UINT8 Reserved93[112]; } FSP_M_CONFIG; /** Fsp M UPD Configuration