diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index 310e6d3bc2..d6b3aff027 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -84,32 +84,44 @@ enum soc_intel_pantherlake_sku {
 	MAX_PTL_SKUS,
 };
 
+/* Thermal Design Current for different SKUs */
+enum soc_intel_pantherlake_tdc {
+	PTL_TDC_1,
+	PTL_TDC_2,
+	PTL_TDC_3,
+	PTL_TDC_4,
+	PTL_TDC_5,
+	WCL_TDC_1,
+	MAX_PTL_TDC
+};
+
 /* Mapping of different SKUs based on CPU ID and TDP values */
 static const struct soc_intel_pantherlake_power_map {
 	unsigned int cpu_id;
 	enum soc_intel_pantherlake_power_limits limits;
 	enum soc_intel_pantherlake_cpu_tdps cpu_tdp;
 	enum soc_intel_pantherlake_sku sku;
+	enum soc_intel_pantherlake_tdc tdc;
 } cpuid_to_ptl[] = {
-	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_CORE_1, TDP_15W, PTL_SKU_1 },
-	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_CORE_1, TDP_25W, PTL_SKU_1 },
-	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_CORE_2, TDP_15W, PTL_SKU_5 },
-	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_CORE_2, TDP_25W, PTL_SKU_5 },
-	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_CORE_1, TDP_15W, PTL_SKU_1 },
-	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_CORE_1, TDP_25W, PTL_SKU_1 },
-	{ PCI_DID_INTEL_PTL_H_ID_1, PTL_CORE_3, TDP_25W, PTL_SKU_2 },
-	{ PCI_DID_INTEL_PTL_H_ID_2, PTL_CORE_3, TDP_25W, PTL_SKU_3 },
-	{ PCI_DID_INTEL_PTL_H_ID_3, PTL_CORE_4, TDP_25W, PTL_SKU_6 },
-	{ PCI_DID_INTEL_PTL_H_ID_4, PTL_CORE_4, TDP_25W, PTL_SKU_6 },
-	{ PCI_DID_INTEL_PTL_H_ID_5, PTL_CORE_4, TDP_25W, PTL_SKU_4 },
-	{ PCI_DID_INTEL_PTL_H_ID_6, PTL_CORE_4, TDP_25W, PTL_SKU_4 },
-	{ PCI_DID_INTEL_PTL_H_ID_7, PTL_CORE_4, TDP_25W, PTL_SKU_4 },
-	{ PCI_DID_INTEL_PTL_H_ID_8, PTL_CORE_3, TDP_25W, PTL_SKU_2 },
-	{ PCI_DID_INTEL_WCL_ID_1, WCL_CORE, TDP_15W, WCL_SKU_1},
-	{ PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_2},
-	{ PCI_DID_INTEL_WCL_ID_3, WCL_CORE, TDP_15W, WCL_SKU_3},
-	{ PCI_DID_INTEL_WCL_ID_4, WCL_CORE, TDP_15W, WCL_SKU_4},
-	{ PCI_DID_INTEL_WCL_ID_5, WCL_CORE, TDP_15W, WCL_SKU_5},
+	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_CORE_1, TDP_15W, PTL_SKU_1, PTL_TDC_1 },
+	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_CORE_1, TDP_25W, PTL_SKU_1, PTL_TDC_2 },
+	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_CORE_2, TDP_15W, PTL_SKU_5, PTL_TDC_1 },
+	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_CORE_2, TDP_25W, PTL_SKU_5, PTL_TDC_2 },
+	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_CORE_1, TDP_15W, PTL_SKU_1, PTL_TDC_1 },
+	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_CORE_1, TDP_25W, PTL_SKU_1, PTL_TDC_2 },
+	{ PCI_DID_INTEL_PTL_H_ID_1, PTL_CORE_3, TDP_25W, PTL_SKU_2, PTL_TDC_3 },
+	{ PCI_DID_INTEL_PTL_H_ID_2, PTL_CORE_3, TDP_25W, PTL_SKU_3, PTL_TDC_4 },
+	{ PCI_DID_INTEL_PTL_H_ID_3, PTL_CORE_4, TDP_25W, PTL_SKU_6, PTL_TDC_3 },
+	{ PCI_DID_INTEL_PTL_H_ID_4, PTL_CORE_4, TDP_25W, PTL_SKU_6, PTL_TDC_3 },
+	{ PCI_DID_INTEL_PTL_H_ID_5, PTL_CORE_4, TDP_25W, PTL_SKU_4, PTL_TDC_5 },
+	{ PCI_DID_INTEL_PTL_H_ID_6, PTL_CORE_4, TDP_25W, PTL_SKU_4, PTL_TDC_5 },
+	{ PCI_DID_INTEL_PTL_H_ID_7, PTL_CORE_4, TDP_25W, PTL_SKU_4, PTL_TDC_5 },
+	{ PCI_DID_INTEL_PTL_H_ID_8, PTL_CORE_3, TDP_25W, PTL_SKU_2, PTL_TDC_3 },
+	{ PCI_DID_INTEL_WCL_ID_1, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
+	{ PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_2, WCL_TDC_1 },
+	{ PCI_DID_INTEL_WCL_ID_3, WCL_CORE, TDP_15W, WCL_SKU_3, WCL_TDC_1 },
+	{ PCI_DID_INTEL_WCL_ID_4, WCL_CORE, TDP_15W, WCL_SKU_4, WCL_TDC_1 },
+	{ PCI_DID_INTEL_WCL_ID_5, WCL_CORE, TDP_15W, WCL_SKU_5, WCL_TDC_1 },
 };
 
 /* Types of display ports */
diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index 676a309f2e..a310a1be3f 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -8,7 +8,11 @@ chip soc/intel/pantherlake
 		.tdp_pl4 = 163,
 		.tdp_pl4_fastvmode = 150,
 	}"
-	register "thermal_design_current[PTL_SKU_1]" = "{
+	register "thermal_design_current[PTL_TDC_1]" = "{
+		[VR_DOMAIN_IA] = 23 * 8,
+		[VR_DOMAIN_GT] = 15 * 8
+	}"
+	register "thermal_design_current[PTL_TDC_2]" = "{
 		[VR_DOMAIN_IA] = 23 * 8,
 		[VR_DOMAIN_GT] = 23 * 8
 	}"
@@ -25,10 +29,6 @@ chip soc/intel/pantherlake
 		.tdp_pl4 = 163,
 		.tdp_pl4_fastvmode = 150,
 	}"
-	register "thermal_design_current[PTL_SKU_5]" = "{
-		[VR_DOMAIN_IA] = 23 * 8,
-		[VR_DOMAIN_GT] = 23 * 8
-	}"
 	register "icc_max[PTL_SKU_5]" = "{
 		[VR_DOMAIN_IA] = 80 * 4,
 		[VR_DOMAIN_GT] = 56 * 4,
@@ -42,7 +42,7 @@ chip soc/intel/pantherlake
 		.tdp_pl4 = 175,
 		.tdp_pl4_fastvmode = 160,
 	}"
-	register "thermal_design_current[PTL_SKU_2]" = "{
+	register "thermal_design_current[PTL_TDC_3]" = "{
 		[VR_DOMAIN_IA] = 31 * 8,
 		[VR_DOMAIN_GT] = 44 * 8
 	}"
@@ -52,7 +52,7 @@ chip soc/intel/pantherlake
 		[VR_DOMAIN_SA] = 56 * 4,
 		[VR_DOMAIN_ATOM] = 30 * 4
 	}"
-	register "thermal_design_current[PTL_SKU_3]" = "{
+	register "thermal_design_current[PTL_TDC_4]" = "{
 		[VR_DOMAIN_IA] = 31 * 8,
 		[VR_DOMAIN_GT] = 23 * 8
 	}"
@@ -64,11 +64,6 @@ chip soc/intel/pantherlake
 		.tdp_pl4_fastvmode = 140
 	}"
 
-
-	register "thermal_design_current[PTL_SKU_6]" = "{
-		[VR_DOMAIN_IA] = 31 * 8,
-		[VR_DOMAIN_GT] = 44 * 8
-	}"
 	register "icc_max[PTL_SKU_6]" = "{
 		[VR_DOMAIN_IA] = 90 * 4,
 		[VR_DOMAIN_GT] = 124 * 4,
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 69f3ed4d9b..63a3f3b013 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -350,10 +350,10 @@ static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg,
 	}
 
 	for (size_t i = 0; i < ARRAY_SIZE(config->thermal_design_current[0]); i++) {
-		if (!config->thermal_design_current[map->sku][i])
+		if (!config->thermal_design_current[map->tdc][i])
 			continue;
 		m_cfg->TdcEnable[i] = 1;
-		m_cfg->TdcCurrentLimit[i] = config->thermal_design_current[map->sku][i];
+		m_cfg->TdcCurrentLimit[i] = config->thermal_design_current[map->tdc][i];
 	}
 
 	for (size_t i = 0; i < ARRAY_SIZE(config->icc_max[0]); i++) {