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mb/{google, intel}: Enable PCH Energy Reporting for MTL platforms

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This patch enables PCH to CPU energy report feature which can be used
by Intel Telemetry Driver.

BUG=b:269563588
TEST=Able to build and boot google/rex and perform below check to ensure
     the energy reporting is correct

w/o this cl:
 # lspci -s 00:14.2 -vvv | grep "Region 0"
    Region 0: Memory at 957f8000 (64-bit, non-prefetchable) [size=16K]
 # iotools mmio_read32 0x957f8068 #i.e., 104th offset
   0xXXXX0000

w/ this cl:
 #lspci -s 00:14.2 -vvv | grep "Region 0"
   Region 0: Memory at 957f8000 (64-bit, non-prefetchable) [size=16K]
 # iotools mmio_read32 0x957f8068 #i.e., 104th offset
  0xXXXXfc004

Change-Id: I9bd4625ea311a05071878aaec68433a1ba018c0d
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76353
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
This commit is contained in:
Sukumar Ghorai 2023-07-06 15:23:32 -07:00 • committed by Felix Held
commit 211e391a82
3 changed files with 10 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

3
src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
View file

@ -33,6 +33,9 @@ chip soc/intel/meteorlake
# S0ix enable
register "s0ix_enable" = "1"
# Enable Energy Reporting
register "pch_pm_energy_report_enable" = "1"
# DPTF enable
register "dptf_enable" = "1"

3
src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
View file

@ -33,6 +33,9 @@ chip soc/intel/meteorlake
# S0ix enable
register "s0ix_enable" = "1"
# Enable Energy Reporting
register "pch_pm_energy_report_enable" = "1"
# DPTF enable
register "dptf_enable" = "1"

4
src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
View file

@ -52,6 +52,9 @@ chip soc/intel/meteorlake
# Enable S0ix
register "s0ix_enable" = "1"
# Enable energy reporting
register "pch_pm_energy_report_enable" = "1"
# Enable EDP in PortA
register "ddi_port_A_config" = "1"
# Enable HDMI in Port B
@ -334,6 +337,7 @@ chip soc/intel/meteorlake
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
}"
end # PCIE11 SSD Gen4
device ref ioe_shared_sram on end
device ref xhci on
chip drivers/usb/acpi
device ref xhci_root_hub on