UPSTREAM: intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP

Change-Id: I9bfaa53f8d09962d36df1e86a0edcf100bb08403
Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15229
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354983
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>

src/cpu/intel/model_6ex/cache_as_ram.inc

@@ -132,7 +132,12 @@ clear_mtrrs:
 	post_code(0x23)
 
 	/* Call romstage.c main function. */
-	call	main
+	call	romstage_main
+
+	/* Save return value from romstage_main. It contains the stack to use
+	 * after cache-as-ram is torn down. It also contains the information
+	 * for setting up MTRRs. */
+	movl	%eax, %ebx
 
 	post_code(0x2f)
 
@@ -219,7 +224,8 @@ __main:
 	post_code(POST_PREPARE_RAMSTAGE)
 	cld			/* Clear direction flag. */
 
-	movl	$CONFIG_RAMTOP, %esp
+	/* Setup stack as indicated by return value from romstage_main(). */
+	movl	%ebx, %esp
 	movl	%esp, %ebp
 	call	copy_and_run
 

src/cpu/intel/socket_BGA956/Makefile.inc

@@ -10,3 +10,4 @@ subdirs-y += ../speedstep
 
 # Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
 cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+romstage-y += ../car/romstage.c

src/cpu/intel/socket_LGA771/Makefile.inc

@@ -9,3 +9,4 @@ subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 
 cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+romstage-y += ../car/romstage.c

src/cpu/intel/socket_LGA775/Makefile.inc

@@ -16,3 +16,4 @@ subdirs-y += ../speedstep
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
 romstage-y += ../car/romstage.c
+romstage-y += ../car/romstage.c

src/cpu/intel/socket_mFCPGA478/Makefile.inc

@@ -12,3 +12,4 @@ subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
 cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+romstage-y += ../car/romstage.c