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UPSTREAM: intel/model_206ax: Prepare for dynamic CONFIG_RAMTOP

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Change-Id: Ib3250677ee926deaa957c83aca7479eb0159358c
Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15231
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/355004
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-06-17 10:00:28 +03:00 • committed by chrome-bot
commit 20d1174f2c
3 changed files with 13 additions and 3 deletions
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5
src/northbridge/intel/sandybridge/romstage.c
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@ -43,7 +43,10 @@ static void early_pch_init(void)
pci_write_config8(PCH_LPC_DEV, 0xa4, reg8);
}
void main(unsigned long bist)
/* Platform has no romstage entry point under mainboard directory,
* so this one is named with prefix mainboard.
*/
void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0;