From 2077d0d79d84bfaede58d81e12639be47a8d33e7 Mon Sep 17 00:00:00 2001 From: Pranava Y N Date: Tue, 1 Apr 2025 17:08:52 +0530 Subject: [PATCH] mb/google/brya/var/redrix: Enable RTD3 for SSD to resolve S0ix issue Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Enable and reset GPIOs are configured as per pin mapping in gpio.c. BUG=b:391612392 TEST=Run suspend_stress_test on redrix device and verify that the device suspends to S0ix. Change-Id: I9d8bd6bb2c5aecf2fa67486cc81935d2ac7cd5ce Signed-off-by: Pranava Y N Reviewed-on: https://review.coreboot.org/c/coreboot/+/87058 Reviewed-by: Jayvik Desai Reviewed-by: Kapil Porwal Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) --- .../google/brya/variants/redrix/overridetree.cb | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 1a9f1d9b17..4b486977c8 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -327,6 +327,15 @@ chip soc/intel/alderlake device generic 0 on end end end #PCIE8 SD card + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "1" + device generic 0 on end + end + end #PCIE9-12 SSD device ref i2c0 on chip drivers/i2c/generic register "hid" = ""RTL5682""