From 2033075753259190e84e89ece6462b9371cadeb9 Mon Sep 17 00:00:00 2001 From: Pranava Y N Date: Wed, 14 May 2025 13:50:06 +0530 Subject: [PATCH] intel/alderlake/romstage: Implement eSOL during EC software sync Move EC software sync to the SoC code when `VBOOT_EC_SYNC_ESOL` config is selected. This allows the early Sign-Of-Life (eSOL) to be displayed during EC firmware update. `VBOOT_EC_SYNC_SOL` is not coupled with `VBOOT_EARLY_EC_SYNC`, therefore it can be enabled only for variants whose EC firmware takes a long time (15-20s) to update. This change also implements `vboot_show_ec_sync_esol()` function that displays the eSOL during the update for Alder Lake devices. AP log during EC firmware update with `VBOOT_EC_SYNC_ESOL` enabled: ``` [INFO ] VB2:check_ec_hash() Heff != Hexp. Schedule update [0.216229] DP PHY mode status not complete [0.217189] DP PHY mode status not complete [INFO ] Informing user on-display of EC software sync. [DEBUG] FMAP: area COREBOOT found @ c0a000 (4153344 bytes) [WARN ] CBFS: 'preram_locales' not found. [INFO ] ux_locales_get_text: preram_locales not found. [INFO ] VB2:sync_ec() select_rw=RW(active) [INFO ] VB2:update_ec() Updating RW(active)... [INFO ] CBFS: Found 'ecrw' @0x1a9f80 size 0x40000 in mcache @0xfef97a9c [INFO ] VB2:vb2_digest_init() 262144 bytes, hash algo 2, HW acceleration enabled [INFO ] CBFS: Found 'ecrw.hash' @0x7f8c0 size 0x20 in mcache @0xfef97708 [INFO ] VB2:vb2_digest_init() 32 bytes, hash algo 2, HW acceleration enabled [INFO ] VB2:check_ec_hash() Hexp RW(active): 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0 [INFO ] VB2:check_ec_hash() Hmir: 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0 [WARN ] ec_hash_image: No valid hash (status=0 size=0). Computing... [INFO ] EC took 482169us to calculate image hash [INFO ] VB2:check_ec_hash() Heff RW(active): 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0 [INFO ] VB2:update_ec() Updated RW(active) successfully [INFO ] VB2:sync_ec() Rebooting to jump to new EC-RW [INFO ] VB2:vb2api_ec_sync() ec_sync_phase2(ctx) returned 0x1004 [INFO ] EC Reboot requested. Doing cold reboot ``` BUG=b:412210635 TEST=Verify successful EC sync in romstage. Verify eSOL is displayed during EC update on a nissa (Alder Lake) board by enabling `VBOOT_EC_SYNC_ESOL` config. Change-Id: I351d464f2ca64a3e60c52f88c8633e05556c5324 Signed-off-by: Pranava Y N Reviewed-on: https://review.coreboot.org/c/coreboot/+/87670 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/romstage/romstage.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index b1ac1caefa..d6a822e440 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #define PSF_UFS0_BASE_ADDRESS 0x280 @@ -172,6 +173,13 @@ void cse_board_reset(void) early_graphics_stop(); } +#if (CONFIG(VBOOT_EC_SYNC_ESOL)) +void vboot_show_ec_sync_esol(void) +{ + ux_inform_user_of_update_operation("EC software sync"); +} +#endif + void mainboard_romstage_entry(void) { struct chipset_power_state *ps = pmc_get_power_state(); @@ -194,6 +202,9 @@ void mainboard_romstage_entry(void) if (!CONFIG(INTEL_TXT)) disable_intel_txt(); + if (CONFIG(VBOOT_EARLY_EC_SYNC) && CONFIG(VBOOT_EC_SYNC_ESOL)) + vboot_sync_ec(); + /* Program to Disable UFS Controllers */ if (!is_devfn_enabled(PCH_DEVFN_UFS) && (CONFIG(USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS))) {