From 1fe88cc716f65bdc990f34895835f26a8e2d6958 Mon Sep 17 00:00:00 2001 From: Sowmya Aralguppe Date: Mon, 2 Feb 2026 12:16:41 +0530 Subject: [PATCH] mb/google/fatcat: Fix fast_vmode_i_trip indexing in devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update fast_vmode_i_trip array references as per 813278_Rev2p1p1 to use PTL_SKU_* constants instead of PTL_CORE_* constants. This aligns with the corrected indexing scheme used in the SoC VR configuration code. TEST=Verify IccLimit value for different SKUs in FSP debug log Change-Id: I90a5c6e03633ba2b4a0a132ed9f94d8e5c4ff8bf Signed-off-by: Sowmya Aralguppe Reviewed-on: https://review.coreboot.org/c/coreboot/+/91049 Reviewed-by: Jérémy Compostella Tested-by: build bot (Jenkins) Reviewed-by: Pranava Y N Reviewed-by: Paul Menzel --- .../variants/baseboard/fatcat/devicetree.cb | 30 ++++++++++++++----- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index 0f74bc79b8..fd1f55fabe 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -87,22 +87,36 @@ chip soc/intel/pantherlake register "cep_enable[VR_DOMAIN_GT]" = "true" register "enable_fast_vmode[VR_DOMAIN_SA]" = "true" register "cep_enable[VR_DOMAIN_SA]" = "true" - register "fast_vmode_i_trip[PTL_CORE_1]" = "{ + register "fast_vmode_i_trip[PTL_SKU_1]" = "{ [VR_DOMAIN_IA] = 63 * 4, [VR_DOMAIN_GT] = 38 * 4, [VR_DOMAIN_SA] = 38 * 4 }" - register "fast_vmode_i_trip[PTL_CORE_2]" = "{ - [VR_DOMAIN_IA] = 63 * 4, - [VR_DOMAIN_GT] = 38 * 4, - [VR_DOMAIN_SA] = 38 * 4 - }" - register "fast_vmode_i_trip[PTL_CORE_3]" = "{ + register "fast_vmode_i_trip[PTL_SKU_2]" = "{ [VR_DOMAIN_IA] = 75 * 4, [VR_DOMAIN_GT] = 75 * 4, [VR_DOMAIN_SA] = 38 * 4 }" - + register "fast_vmode_i_trip[PTL_SKU_3]" = "{ + [VR_DOMAIN_IA] = 75 * 4, + [VR_DOMAIN_GT] = 38 * 4, + [VR_DOMAIN_SA] = 38 * 4 + }" + register "fast_vmode_i_trip[PTL_SKU_5]" = "{ + [VR_DOMAIN_IA] = 63 * 4, + [VR_DOMAIN_GT] = 38 * 4, + [VR_DOMAIN_SA] = 38 * 4 + }" + register "fast_vmode_i_trip[PTL_SKU_6]" = "{ + [VR_DOMAIN_IA] = 75 * 4, + [VR_DOMAIN_GT] = 75 * 4, + [VR_DOMAIN_SA] = 38 * 4 + }" + register "fast_vmode_i_trip[PTL_SKU_7]" = "{ + [VR_DOMAIN_IA] = 75 * 4, + [VR_DOMAIN_GT] = 38 * 4, + [VR_DOMAIN_SA] = 38 * 4 + }" # Set on-board graphics as primary display register "skip_ext_gfx_scan" = "true"