erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

UPSTREAM: soc/intel/quark: Switch to using serial routines for FSP

Browse source 
Switch from passing FSP the serial port address to passing FSP the
serial port output routine.  This enables coreboot to use any UART in
the system and also log the FSP output.

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16105
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I67d820ea0360a3188480455dd2595be7f2debd5c
Reviewed-on: https://chromium-review.googlesource.com/369116
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lee Leahy 2016-08-06 09:51:35 -07:00 • committed by chrome-bot
commit 1fcaa4622a
4 changed files with 41 additions and 16 deletions
Download patch file Download diff file Expand all files Collapse all files

21
src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
View file

@ -88,7 +88,7 @@ typedef struct {
UINT32 RmuLength;
/** Offset 0x0030
**/
UINT32 SerialPortBaseAddress;
UINT32 Reserved_30;
/** Offset 0x0034
**/
UINT32 tRAS;
@ -175,17 +175,26 @@ typedef struct {
UINT32 MrcDataLength;
/** Offset 0x0068
**/
UINT8 ReservedMemoryInitUpd[8];
UINT32 SerialPortPollForChar;
/** Offset 0x006C
**/
UINT32 SerialPortReadChar;
/** Offset 0x0070
**/
UINT32 SerialPortWriteChar;
/** Offset 0x0074
**/
UINT8 ReservedMemoryInitUpd[12];
} MEMORY_INIT_UPD;
typedef struct {
/** Offset 0x0070
/** Offset 0x0080
**/
UINT64 Signature;
/** Offset 0x0078
/** Offset 0x0088
**/
UINT64 Revision;
/** Offset 0x0080
/** Offset 0x0090
**/
UINT16 PcdRegionTerminator;
} SILICON_INIT_UPD;
@ -210,7 +219,7 @@ typedef struct _UPD_DATA_REGION {
/** Offset 0x0018
**/
MEMORY_INIT_UPD MemoryInitUpd;
/** Offset 0x0070
/** Offset 0x0080
**/
SILICON_INIT_UPD SiliconInitUpd;
} UPD_DATA_REGION;