From 1fb659b3e73285ff8218c0f229734edd3b979ca4 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Fri, 8 Nov 2013 17:49:26 +0800 Subject: [PATCH] nyan: Enable and configure clocks for I2S and audio codec. To enable audio playback, the I2S (currently only I2S1 is configured) and audio codec (external peripheral 1) must be first configured. Note due to Tegra1x4 audio hardware design, we need to enable all audio peripherals on AHUB. BUG=none TEST=emerge-nyan chromeos-coreboot-nyan; Able to readl(I2Sreg). BRANCH=none Change-Id: Ie5c8a95f385305870745af7aeb40d7f7da8bbc0b Signed-off-by: Hung-Te Lin Reviewed-on: https://chromium-review.googlesource.com/176104 Reviewed-by: Gabe Black Reviewed-by: Tom Warren --- src/mainboard/google/nyan/mainboard.c | 41 ++++++++++++++++++--- src/soc/nvidia/tegra124/include/soc/clock.h | 7 ++++ 2 files changed, 43 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index 5c9d03f101..2dfe6252af 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -48,6 +48,16 @@ static void set_clock_sources(void) clock_configure_source(sdmmc3, PLLP, 48000); clock_configure_source(sdmmc4, PLLP, 48000); + /* External peripheral 1: audio codec (max98090) using 12MHz CLK1. + * Note the source id of CLK_M for EXTPERIPH1 is 3. */ + clock_configure_irregular_source(extperiph1, CLK_M, 12000, 3); + + /* + * I2S1 can use either PLLP or PLLA. Using PLLP is sufficient now since + * we only need 4.8MHz. Note the source id of PLLP for I2S is 4. + */ + clock_configure_irregular_source(i2s1, PLLP, 4800, 4); + /* Note source id of PLLP for HOST1x is 4. */ clock_configure_irregular_source(host1x, PLLP, 408000, 4); @@ -199,14 +209,35 @@ static void setup_ec_spi(void) static void mainboard_init(device_t dev) { set_clock_sources(); - clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | - CLK_L_SDMMC4 | CLK_L_USBD | - CLK_L_DISP1 | CLK_L_HOST1X, + + clock_external_output(1); /* For external MAX98090 audio codec. */ + + /* + * Confirmed by NVIDIA hardware team, we need to take ALL audio devices + * conntected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out + * of reset and clock-enabled, otherwise reading AHUB devices (In our + * case, I2S/APBIF/AUDIO) will hang. + */ + clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | CLK_L_SDMMC4 | + CLK_L_I2S0 | CLK_L_I2S1 | CLK_L_I2S2 | + CLK_L_SPDIF | CLK_L_USBD | CLK_L_DISP1 | + CLK_L_HOST1X, + CLK_H_EMC | CLK_H_I2C2 | CLK_H_SBC1 | CLK_H_PMC | CLK_H_MEM | CLK_H_USB3, + CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3, - CLK_V_I2C4, - CLK_W_DVFS, CLK_X_DPAUX | CLK_X_SOR0); + + CLK_V_I2C4 | CLK_V_EXTPERIPH1 | CLK_V_APBIF | + CLK_V_AUDIO | CLK_V_I2S3 | CLK_V_I2S4 | + CLK_V_DAM0 | CLK_V_DAM1 | CLK_V_DAM2, + + CLK_W_DVFS | CLK_W_AMX0 | CLK_W_ADX0, + + CLK_X_DPAUX | CLK_X_SOR0 | CLK_X_AMX1 | + CLK_X_ADX1 | CLK_X_AFC0 | CLK_X_AFC1 | + CLK_X_AFC2 | CLK_X_AFC3 | CLK_X_AFC4 | + CLK_X_AFC5); usb_setup_utmip1(); /* USB2 is the camera, we don't need it in firmware */ diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h index 75acdb9bcc..3eec82c733 100644 --- a/src/soc/nvidia/tegra124/include/soc/clock.h +++ b/src/soc/nvidia/tegra124/include/soc/clock.h @@ -129,6 +129,7 @@ enum { CLK_V_HDA2CODEC_2X = 0x1 << 15, CLK_V_ATOMICS = 0x1 << 16, CLK_V_ACTMON = 0x1 << 23, + CLK_V_EXTPERIPH1 = 0x1 << 24, CLK_V_SATA = 0x1 << 28, CLK_V_HDA = 0x1 << 29, @@ -144,6 +145,12 @@ enum { CLK_W_MC1 = 0x1 << 30, CLK_W_EMC1 = 0x1 << 31, + CLK_X_AFC0 = 0x1 << 31, + CLK_X_AFC1 = 0x1 << 30, + CLK_X_AFC2 = 0x1 << 29, + CLK_X_AFC3 = 0x1 << 28, + CLK_X_AFC4 = 0x1 << 27, + CLK_X_AFC5 = 0x1 << 26, CLK_X_AMX1 = 0x1 << 25, CLK_X_GPU = 0x1 << 24, CLK_X_SOR0 = 0x1 << 22,