move smbus_read to spd_read_byte. Add debug prints. These debug prints
and hcf may move to a common library later. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@528 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich
parent
9df08251e0
commit
1f4286cc5a
1 changed files with 80 additions and 24 deletions
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@ -33,6 +33,39 @@ static const u8 num_col_addr[] = {
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0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
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};
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u8 spd_read_byte(u16 device, u8 address);
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/**
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* Print a nice banner so we know what step we died on.
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*
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* @param s String to put in the middle of the banner
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*/
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void banner(char *s)
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{
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printk(BIOS_DEBUG, "===========================");
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printk(BIOS_DEBUG, s);
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printk(BIOS_DEBUG, "======================================\n");
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}
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/**
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* Halt and Catch Fire. Print an error, then loop, sending NULLs on serial port,
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* to ensure the message is visible.
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*
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*/
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void hcf(void)
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{
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printk(BIOS_EMERG, "DIE\r\n");
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/* this guarantees we flush the UART fifos (if any) and also
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* ensures that things, in general, keep going so no debug output
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* is lost
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*/
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while (1)
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printk(BIOS_EMERG, "\r");
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}
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/**
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* Auto-detect, using SPD, the DIMM size. It's the usual magic, with
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* all the usual failure points that can happen.
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@ -50,11 +83,15 @@ static void auto_size_dimm(unsigned int dimm, u8 dimm0, u8 dimm1)
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dimm_setting = 0;
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banner("Check present");
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/* Check that we have a DIMM. */
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if (smbus_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF)
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if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF)
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return;
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spd_byte = smbus_read_byte(dimm, SPD_NUM_DIMM_BANKS);
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/* Field: Module Banks per DIMM */
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/* EEPROM byte usage: (5) Number of DIMM Banks */
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banner("MODBANKS");
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spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
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if ((MIN_MOD_BANKS > spd_byte) && (spd_byte > MAX_MOD_BANKS)) {
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printk(BIOS_EMERG, "Number of module banks not compatible\n");
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post_code(ERROR_BANK_SET);
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@ -62,7 +99,10 @@ static void auto_size_dimm(unsigned int dimm, u8 dimm0, u8 dimm1)
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}
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dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
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spd_byte = smbus_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
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/* Field: Banks per SDRAM device */
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/* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
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banner("FIELDBANKS");
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spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
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if ((MIN_DEV_BANKS > spd_byte) && (spd_byte > MAX_DEV_BANKS)) {
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printk(BIOS_EMERG, "Number of device banks not compatible\n");
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post_code(ERROR_BANK_SET);
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@ -70,15 +110,25 @@ static void auto_size_dimm(unsigned int dimm, u8 dimm0, u8 dimm1)
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}
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dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
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if ((smbus_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
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|| (smbus_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
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/*; Field: DIMM size
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*; EEPROM byte usage: (3) Number of Row Addresses
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*; (4) Number of Column Addresses
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*; (5) Number of DIMM Banks
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*; (31) Module Bank Density
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*; Size = Module Density * Module Banks
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*/
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banner("SPDNUMROWS");
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if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
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|| (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
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printk(BIOS_EMERG, "Asymmetric DIMM not compatible\n");
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post_code(ERROR_UNSUPPORTED_DIMM);
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hlt();
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}
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/* Size = Module Density * Module Banks */
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dimm_size = smbus_read_byte(dimm, SPD_BANK_DENSITY);
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banner("SPDBANKDENSITY");
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dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY);
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/* Align so 1 GB (bit 0) is bit 8. This is a little weird to get gcc
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* to not optimize this out.
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@ -93,7 +143,9 @@ static void auto_size_dimm(unsigned int dimm, u8 dimm0, u8 dimm1)
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/* Module Density * Module Banks */
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/* Shift to multiply by the number of DIMM banks. */
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dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1;
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banner("BEFORT CTZ");
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dimm_size = __builtin_ctz(dimm_size);
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banner("TEST DIMM SIZE>8");
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if (dimm_size > 8) { /* 8 is 1 GB only support 1 GB per DIMM */
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printk(BIOS_EMERG, "Only support up to 1 GB per DIMM\n");
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post_code(ERROR_DENSITY_DIMM);
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@ -125,8 +177,9 @@ static void auto_size_dimm(unsigned int dimm, u8 dimm0, u8 dimm1)
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* example, #col_addr_bits = 7 (06h), it adds 3 to get 10, then does
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* 2^10=1K. Get it?
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*/
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spd_byte = num_col_addr[smbus_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
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banner("PAGESIZE");
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spd_byte = num_col_addr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
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banner("MAXCOLADDR");
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if (spd_byte > MAX_COL_ADDR) {
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printk(BIOS_EMERG, "DIMM page size not compatible\n");
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post_code(ERROR_SET_PAGE);
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@ -140,7 +193,9 @@ static void auto_size_dimm(unsigned int dimm, u8 dimm0, u8 dimm1)
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/* 0 = 1k, 1 = 2k, 2 = 4k, etc. */
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dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT;
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banner("RDMSR CF07");
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msr = rdmsr(MC_CF07_DATA);
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banner("WRMSR CF07");
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if (dimm == dimm0) {
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msr.hi &= 0xFFFF0000;
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msr.hi |= dimm_setting;
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@ -148,6 +203,7 @@ static void auto_size_dimm(unsigned int dimm, u8 dimm0, u8 dimm1)
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msr.hi &= 0x0000FFFF;
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msr.hi |= dimm_setting << 16;
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}
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banner("ALL DONE");
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wrmsr(MC_CF07_DATA, msr);
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}
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@ -166,10 +222,10 @@ static void check_ddr_max(u8 dimm0, u8 dimm1)
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u16 speed;
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/* PC133 identifier */
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spd_byte0 = smbus_read_byte(dimm0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
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spd_byte0 = spd_read_byte(dimm0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
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if (spd_byte0 == 0xFF)
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spd_byte0 = 0;
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spd_byte1 = smbus_read_byte(dimm1, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
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spd_byte1 = spd_read_byte(dimm1, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
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if (spd_byte1 == 0xFF)
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spd_byte1 = 0;
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@ -213,13 +269,13 @@ static void set_refresh_rate(u8 dimm0, u8 dimm1)
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u16 rate0, rate1;
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struct msr msr;
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spd_byte0 = smbus_read_byte(dimm0, SPD_REFRESH);
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spd_byte0 = spd_read_byte(dimm0, SPD_REFRESH);
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spd_byte0 &= 0xF;
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if (spd_byte0 > 5)
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spd_byte0 = 5;
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rate0 = REFRESH_RATE[spd_byte0];
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spd_byte1 = smbus_read_byte(dimm1, SPD_REFRESH);
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spd_byte1 = spd_read_byte(dimm1, SPD_REFRESH);
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spd_byte1 &= 0xF;
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if (spd_byte1 > 5)
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spd_byte1 = 5;
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@ -268,11 +324,11 @@ static void set_cas(u8 dimm0, u8 dimm1)
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glspeed = geode_link_speed();
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/* DIMM 0 */
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casmap0 = smbus_read_byte(dimm0, SPD_ACCEPTABLE_CAS_LATENCIES);
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casmap0 = spd_read_byte(dimm0, SPD_ACCEPTABLE_CAS_LATENCIES);
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if (casmap0 != 0xFF) {
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/* If -.5 timing is supported, check -.5 timing > GeodeLink. */
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/* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5 */
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spd_byte = smbus_read_byte(dimm0, SPD_SDRAM_CYCLE_TIME_2ND);
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spd_byte = spd_read_byte(dimm0, SPD_SDRAM_CYCLE_TIME_2ND);
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if (spd_byte != 0) {
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/* Turn SPD ns time into MHz. Check what the asm does
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* to this math.
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@ -282,7 +338,7 @@ static void set_cas(u8 dimm0, u8 dimm1)
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if (dimm_speed >= glspeed) {
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/* If -1 timing is supported, check -1 timing > GeodeLink. */
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/* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1 */
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spd_byte = smbus_read_byte(dimm0, SPD_SDRAM_CYCLE_TIME_3RD);
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spd_byte = spd_read_byte(dimm0, SPD_SDRAM_CYCLE_TIME_3RD);
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if (spd_byte != 0) {
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/* Turn SPD ns time into MHz. Check what the asm does to this math. */
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dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
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@ -305,18 +361,18 @@ static void set_cas(u8 dimm0, u8 dimm1)
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}
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/* DIMM 1 */
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casmap1 = smbus_read_byte(dimm1, SPD_ACCEPTABLE_CAS_LATENCIES);
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casmap1 = spd_read_byte(dimm1, SPD_ACCEPTABLE_CAS_LATENCIES);
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if (casmap1 != 0xFF) {
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/* If -.5 timing is supported, check -.5 timing > GeodeLink. */
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/* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5 */
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spd_byte = smbus_read_byte(dimm1, SPD_SDRAM_CYCLE_TIME_2ND);
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spd_byte = spd_read_byte(dimm1, SPD_SDRAM_CYCLE_TIME_2ND);
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if (spd_byte != 0) {
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/* Turn SPD ns time into MHz. Check what the asm does to this math. */
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dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
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if (dimm_speed >= glspeed) {
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/* If -1 timing is supported, check -1 timing > GeodeLink. */
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/* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1 */
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spd_byte = smbus_read_byte(dimm1, SPD_SDRAM_CYCLE_TIME_3RD);
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spd_byte = spd_read_byte(dimm1, SPD_SDRAM_CYCLE_TIME_3RD);
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if (spd_byte != 0) {
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/* Turn SPD ns time into MHz. Check what the asm does to this math. */
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dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
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@ -359,10 +415,10 @@ static void set_cas(u8 dimm0, u8 dimm1)
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static inline void helper_spd(u8 dimm0, u8 dimm1, u8 addr, u8 *spd0, u8 *spd1)
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{
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*spd0 = smbus_read_byte(dimm0, addr);
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*spd0 = spd_read_byte(dimm0, addr);
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if (*spd0 == 0xFF)
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*spd0 = 0;
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*spd1 = smbus_read_byte(dimm1, addr);
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*spd1 = spd_read_byte(dimm1, addr);
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if (*spd1 == 0xFF)
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*spd1 = 0;
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if (*spd0 < *spd1)
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@ -477,10 +533,10 @@ static void set_extended_mode_registers(u8 dimm0, u8 dimm1)
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u8 spd_byte0, spd_byte1;
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struct msr msr;
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spd_byte0 = smbus_read_byte(dimm0, SPD_DEVICE_ATTRIBUTES_GENERAL);
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spd_byte0 = spd_read_byte(dimm0, SPD_DEVICE_ATTRIBUTES_GENERAL);
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if (spd_byte0 == 0xFF)
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spd_byte0 = 0;
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spd_byte1 = smbus_read_byte(dimm1, SPD_DEVICE_ATTRIBUTES_GENERAL);
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spd_byte1 = spd_read_byte(dimm1, SPD_DEVICE_ATTRIBUTES_GENERAL);
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if (spd_byte1 == 0xFF)
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spd_byte1 = 0;
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spd_byte1 &= spd_byte0;
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@ -558,7 +614,7 @@ void sdram_set_spd_registers(u8 dimm0, u8 dimm1)
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post_code(POST_MEM_SETUP);
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spd_byte = smbus_read_byte(dimm0, SPD_MODULE_ATTRIBUTES);
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spd_byte = spd_read_byte(dimm0, SPD_MODULE_ATTRIBUTES);
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/* Check DIMM is not Registered and not Buffered DIMMs. */
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if ((spd_byte != 0xFF) && (spd_byte & 3)) {
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@ -566,7 +622,7 @@ void sdram_set_spd_registers(u8 dimm0, u8 dimm1)
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post_code(ERROR_UNSUPPORTED_DIMM);
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hlt();
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}
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spd_byte = smbus_read_byte(dimm1, SPD_MODULE_ATTRIBUTES);
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spd_byte = spd_read_byte(dimm1, SPD_MODULE_ATTRIBUTES);
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if ((spd_byte != 0xFF) && (spd_byte & 3)) {
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printk(BIOS_EMERG, "DIMM 1 NOT COMPATIBLE!\n");
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post_code(ERROR_UNSUPPORTED_DIMM);
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