From 1f1a76c8ff3b2309abc8a0cb1bec55e2ebdbb172 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 9 Sep 2013 11:12:46 -0700 Subject: [PATCH] Drop non-dynamic CBMEM support from ARM mainboards All ARM systems we support have dynamic CBMEM support. Hence drop non-dynamic CBMEM support from the mainboard specific code. BUG=none BRANCH=none TEST=boot tested on pit Change-Id: Icdff8dd8306ca40f86f08dee2a65f03a526b99db Signed-off-by: Stefan Reinauer Reviewed-on: https://chromium-review.googlesource.com/168573 Reviewed-by: Gabe Black --- src/mainboard/google/kirby/mainboard.c | 10 ---------- src/mainboard/google/pit/mainboard.c | 10 ---------- src/mainboard/google/snow/mainboard.c | 10 ---------- 3 files changed, 30 deletions(-) diff --git a/src/mainboard/google/kirby/mainboard.c b/src/mainboard/google/kirby/mainboard.c index ecbfb2a0bf..56ade8a3d8 100644 --- a/src/mainboard/google/kirby/mainboard.c +++ b/src/mainboard/google/kirby/mainboard.c @@ -430,16 +430,6 @@ static void mainboard_enable(device_t dev) { dev->ops->init = &mainboard_init; -#if !CONFIG_DYNAMIC_CBMEM - /* set up coreboot tables */ - /* FIXME: this should happen somewhere else */ - high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; - high_tables_base = CONFIG_SYS_SDRAM_BASE + - ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - - CONFIG_COREBOOT_TABLES_SIZE; - cbmem_init(high_tables_base, high_tables_size); -#endif - /* set up caching for the DRAM */ mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF); diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index 0835866b58..bdf2d571b2 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -453,16 +453,6 @@ static void mainboard_enable(device_t dev) { dev->ops->init = &mainboard_init; -#if !CONFIG_DYNAMIC_CBMEM - /* set up coreboot tables */ - /* FIXME: this should happen somewhere else */ - high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; - high_tables_base = CONFIG_SYS_SDRAM_BASE + - ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - - CONFIG_COREBOOT_TABLES_SIZE; - cbmem_init(high_tables_base, high_tables_size); -#endif - /* set up caching for the DRAM */ mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF); diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index 1a286341bd..756dc15325 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -317,16 +317,6 @@ static void mainboard_enable(device_t dev) { dev->ops->init = &mainboard_init; -#if !CONFIG_DYNAMIC_CBMEM - /* set up coreboot tables */ - /* FIXME: this should happen somewhere else */ - high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; - high_tables_base = CONFIG_SYS_SDRAM_BASE + - ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - - CONFIG_COREBOOT_TABLES_SIZE; - cbmem_init(high_tables_base, high_tables_size); -#endif - /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */ exynos5250_config_l2_cache();