From 1ec46a45c4c7c41320943b50dbbb1c3b16dcc458 Mon Sep 17 00:00:00 2001 From: Pranava Y N Date: Mon, 3 Mar 2025 11:54:29 +0530 Subject: [PATCH] mb/google/brya/constitution: Enable RTD3 for SSD to resolve S0ix issue Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Enable and reset GPIOs are configured as per pin mapping in gpio.c. BUG=b:391612392 TEST=Run suspend_stress_test on constitution device and verify that the device suspends to S0ix. Change-Id: Ia367911d6d55b1f769c1660a6f42118988975621 Signed-off-by: Pranava Y N Reviewed-on: https://review.coreboot.org/c/coreboot/+/86686 Reviewed-by: Kapil Porwal Reviewed-by: Eric Lai Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- .../google/brya/variants/constitution/overridetree.cb | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/google/brya/variants/constitution/overridetree.cb b/src/mainboard/google/brya/variants/constitution/overridetree.cb index 01e4a15a75..f6c5380586 100644 --- a/src/mainboard/google/brya/variants/constitution/overridetree.cb +++ b/src/mainboard/google/brya/variants/constitution/overridetree.cb @@ -145,6 +145,13 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end end device ref tcss_dma0 on chip drivers/intel/usb4/retimer