diff --git a/src/soc/mediatek/common/dp/dptx_hal_common.c b/src/soc/mediatek/common/dp/dptx_hal_common.c
index c2d6986309..4ef07ac327 100644
--- a/src/soc/mediatek/common/dp/dptx_hal_common.c
+++ b/src/soc/mediatek/common/dp/dptx_hal_common.c
@@ -54,7 +54,7 @@ void mtk_dp_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask)
 	clrsetbits32(addr, mask, val & mask);
 }
 
-void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u32 mask)
+void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u8 mask)
 {
 	if (addr % 2) {
 		mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x12);
diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h
index 7ed41e81b6..7f0e30f38c 100644
--- a/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h
+++ b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h
@@ -69,7 +69,7 @@ u32 mtk_dp_phy_read(struct mtk_dp *mtk_dp, u32 offset);
 void mtk_dp_phy_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask);
 void mtk_dp_phy_write(struct mtk_dp *mtk_dp, u32 offset, u32 val);
 u32 mtk_dp_read(struct mtk_dp *mtk_dp, u32 offset);
-void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u32 mask);
+void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u8 mask);
 void mtk_dp_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask);
 void mtk_dp_write(struct mtk_dp *mtk_dp, u32 offset, u32 val);
 void dptx_hal_verify_clock(struct mtk_dp *mtk_dp);