From 1e50d15b570e941f5853536804f317f6d174b7ea Mon Sep 17 00:00:00 2001 From: "Eric W. Biederman" Date: Fri, 25 Oct 2002 20:39:20 +0000 Subject: [PATCH] - New secondary.S - Merge supermicro mainboard directories --- src/arch/i386/smp/secondary.S | 21 +-- src/mainboard/supermicro/p4dc6/mainboard.c | 13 +- src/mainboard/supermicro/p4dc6p/mainboard.c | 6 +- src/mainboard/supermicro/p4dpe/Config | 77 ++++----- src/mainboard/supermicro/p4dpe/irq_tables.c | 34 ++-- src/mainboard/supermicro/p4dpe/mainboard.c | 117 +------------ src/mainboard/supermicro/p4dpe/mptable.c | 176 +++++++++++++------- src/mainboard/supermicro/p4dpr/Config | 73 ++++---- src/mainboard/supermicro/p4dpr/mainboard.c | 117 +------------ src/mainboard/supermicro/p4dpr/mptable.c | 168 +++++++------------ 10 files changed, 285 insertions(+), 517 deletions(-) diff --git a/src/arch/i386/smp/secondary.S b/src/arch/i386/smp/secondary.S index 149f8880a8..d702332fca 100644 --- a/src/arch/i386/smp/secondary.S +++ b/src/arch/i386/smp/secondary.S @@ -1,9 +1,8 @@ -.text -#include -#include #include #include - +#include +#include + .text .globl _secondary_start .balign 4096 _secondary_start: @@ -45,9 +44,6 @@ _secondary_start: orl $APIC_DEFAULT_BASE, %eax wrmsr - /* Do I want to set the absolute memory limits in C ? */ - CALLSP(set_memory_size) - /* Get the apic_id */ movl (APIC_ID + APIC_DEFAULT_BASE), %edi shrl $24, %edi @@ -69,11 +65,12 @@ _secondary_start: subl %eax, %esp call EXT(secondary_cpu_init) - jmp __cpu_reset +1: hlt + jmp 1b gdtaddr: - .word gdt_end - gdt - 1 /* compute the table limit */ - .long gdt /* we know the offset */ - -.previous + .word gdt_limit /* the table limit */ + .long gdt /* we know the offset */ + + .code32 diff --git a/src/mainboard/supermicro/p4dc6/mainboard.c b/src/mainboard/supermicro/p4dc6/mainboard.c index b712ea0249..2e979b9c82 100644 --- a/src/mainboard/supermicro/p4dc6/mainboard.c +++ b/src/mainboard/supermicro/p4dc6/mainboard.c @@ -42,11 +42,11 @@ static void set_power_on_after_power_fail(int setting) case MAINBOARD_POWER_ON: default: ich2_power_after_power_fail(1); - w832627hf_power_after_power_fail(POWER_ON); + w83627hf_power_after_power_fail(POWER_ON); break; case MAINBOARD_POWER_OFF: ich2_power_after_power_fail(0); - w832627hf_power_after_power_fail(POWER_OFF); + w83627hf_power_after_power_fail(POWER_OFF); break; } @@ -55,6 +55,8 @@ void mainboard_fixup(void) { int cpu_clock_multiplier; int power_on_after_power_fail; + + w83627hf_power_led(LED_ON); ich2_enable_ioapic(); ich2_enable_serial_irqs(); ich2_enable_ide(1,1); @@ -161,11 +163,4 @@ void cache_ram_start(void) } else { printk_info("Leaving cacheram...\n"); } - } - - - - - - diff --git a/src/mainboard/supermicro/p4dc6p/mainboard.c b/src/mainboard/supermicro/p4dc6p/mainboard.c index f1ad1cf3e4..83f617d1a6 100644 --- a/src/mainboard/supermicro/p4dc6p/mainboard.c +++ b/src/mainboard/supermicro/p4dc6p/mainboard.c @@ -44,11 +44,11 @@ static void set_power_on_after_power_fail(int setting) case MAINBOARD_POWER_ON: default: ich2_power_after_power_fail(1); - w832627hf_power_after_power_fail(POWER_ON); + w83627hf_power_after_power_fail(POWER_ON); break; case MAINBOARD_POWER_OFF: ich2_power_after_power_fail(0); - w832627hf_power_after_power_fail(POWER_OFF); + w83627hf_power_after_power_fail(POWER_OFF); break; } @@ -74,6 +74,8 @@ void mainboard_fixup(void) int cpu_clock_multiplier; int power_on_after_power_fail; int thermal_monitoring; + + w83627hf_power_led(LED_ON); ich2_enable_ioapic(); ich2_enable_serial_irqs(); ich2_enable_ide(1,1); diff --git a/src/mainboard/supermicro/p4dpe/Config b/src/mainboard/supermicro/p4dpe/Config index 104ffe3b0f..2e820c5c4f 100644 --- a/src/mainboard/supermicro/p4dpe/Config +++ b/src/mainboard/supermicro/p4dpe/Config @@ -11,11 +11,6 @@ mainboardinit cpu/i386/entry32.inc ldscript cpu/i386/entry16.lds ldscript cpu/i386/entry32.lds -## -## Test for logical cpu thats not BSP -## -mainboardinit cpu/i786/logical_cpu.inc USE_FALLBACK_IMAGE - ## ## Build our reset vector (This is where linuxBIOS is entered) ## @@ -30,24 +25,18 @@ ldscript cpu/i386/reset32.lds USE_NORMAL_IMAGE mainboardinit arch/i386/lib/id.inc ldscript arch/i386/lib/id.lds -## -## Startup code for secondary CPUS -## -# mainboardinit arch/i386/smp/secondary.inc - ## This is the early phase of linuxBIOS startup ## Things are delicate and we test to see if we should ## failover to another image. -mainboardinit northbridge/intel/82860/reset_test.inc +mainboardinit northbridge/intel/E7500/reset_test.inc mainboardinit arch/i386/lib/noop_failover.inc USE_NORMAL_IMAGE -mainboardinit southbridge/intel/82801/cmos_failover.inc USE_FALLBACK_IMAGE +mainboardinit southbridge/intel/82801ca/cmos_failover.inc USE_FALLBACK_IMAGE ldscript arch/i386/lib/failover.lds USE_FALLBACK_IMAGE ### ### O.k. We aren't just an intermediary anymore! ### - ## ## Setup our mtrrs ## @@ -59,28 +48,31 @@ mainboardinit cpu/i786/earlymtrr.inc mainboardinit superio/winbond/w83627hf/setup_serial.inc mainboardinit pc80/serial.inc mainboardinit arch/i386/lib/console.inc +mainboardinit southbridge/intel/82801ca/watchdog_disable.inc ## -## Switch temporarily into C code to setup RAM +## Reset pci clock for hardware bug work around ## -#mainboardinit cpu/i786/cache_ram_init.inc -## mainboardinit cpu/i786/cache_ram_test.inc -#mainboardinit cpu/i786/cache_ram_start.inc -#mainboardinit cpu/i786/cache_ram_fini.inc -#ldscript cpu/i786/cache_ram.lds +mainboardinit southbridge/intel/82801ca/smbus.inc +mainboardinit southbridge/intel/82801ca/smbus_write_block.inc +mainboardinit mainboard/supermicro/p4dpe/pci_clk_reset.inc -mainboardinit ram/ramtest.inc -option RAMTEST=1 -mainboardinit ram/dump_northbridge.inc +## +## Smbus functions +## +mainboardinit southbridge/intel/82801ca/smbus_read_byte.inc +#mainboardinit southbridge/intel/82801ca/smbus_read_block.inc +#mainboardinit southbridge/intel/82801ca/smbus_print_block.inc +mainboardinit mainboard/supermicro/p4dpe/select_i2c_spd.inc ## ## Setup RAM ## -#mainboardinit southbridge/intel/82801/smbus.inc +mainboardinit ram/spotcheck.inc +#mainboardinit ram/dump_northbridge.inc +#mainboardinit sdram/generic_dump_smbus.inc #mainboardinit sdram/generic_dump_spd.inc mainboardinit mainboard/supermicro/p4dpe/mainboard_raminit.inc -mainboardinit ram/spotcheck.inc - ## ## Include the secondary Configuration files @@ -88,7 +80,7 @@ mainboardinit ram/spotcheck.inc northbridge intel/E7500 southbridge intel/82801ca southbridge intel/82870 -nsuperio winbond/w83627hf com1={1} com2={1} floppy=1 lpt=1 keyboard=1 +nsuperio winbond/w83627hf com1={1} com2={1} floppy=1 lpt=1 keyboard=1 hwmonitor=1 dir /src/pc80 dir /src/superio/winbond/w83627hf dir /src/ram/ @@ -100,7 +92,7 @@ cpu i786 ## Build the objects we have code for in this directory. ## object mainboard.o -object mtrr_values.o +#object devices.o object mptable.o HAVE_MP_TABLE object irq_tables.o HAVE_PIRQ_TABLE @@ -118,7 +110,6 @@ option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +3) option SMBUS_MEM_DEVICE_INC=1 option SMBUS_MEM_CHANNEL_OFF=4 - ## ## Customize our winbond superio chip for this motherboard ## @@ -133,7 +124,14 @@ option HAVE_FALLBACK_BOOT=1 ## ## Build code for using cache as RAM ## -option USE_CACHE_RAM=1 +#option USE_CACHE_RAM=0 + +## +## Delay timer options +## +option CONFIG_UDELAY_TSC=1 +option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + ## ## Build code to reset the motherboard from linuxBIOS @@ -186,22 +184,6 @@ option IOAPIC=1 ## nooption MEMORY_HOLE -## -## Don't do a generic MTRR setup -## Instead use values from the fixed_mtrr_values array -## -option HAVE_MTRR_TABLE=1 - -## -## Enable both fixed and variable MTRRS -## When we setup MTRRs in mtrr.c -## -## We must setup the fixed mtrrs or we confuse SMP secondary -## processor identification -## -option ENABLE_FIXED_AND_VARIABLE_MTRRS=1 - - ## ## Figure out which type of linuxBIOS image to build ## If we aren't a fallback image we must be a normal image @@ -241,9 +223,12 @@ option HEAP_SIZE=0x2000 ## ## Clean up the motherboard id strings ## -option MAINBOARD_PART_NUMBER=P4DPR +option MAINBOARD_PART_NUMBER=P4DP6 option MAINBOARD_VENDOR=Supermicro +option UPDATE_MICROCODE=1 +option CPU_FIXUP=1 + ## ## Only use the option table in a normal image ## diff --git a/src/mainboard/supermicro/p4dpe/irq_tables.c b/src/mainboard/supermicro/p4dpe/irq_tables.c index 0c23b742a9..d1b0947386 100644 --- a/src/mainboard/supermicro/p4dpe/irq_tables.c +++ b/src/mainboard/supermicro/p4dpe/irq_tables.c @@ -1,11 +1,11 @@ -/* PCI: Interrupt Routing Table found at 0x4011ce40 size = 416 */ +/* PCI: Interrupt Routing Table found at 0x4011ce00 size = 480 */ #include const struct irq_routing_table intel_irq_routing_table = { 0x52495024, /* u32 signature */ 0x0100, /* u16 version */ - 416, /* u16 Table size 32+(16*devices) */ + 480, /* u16 Table size 32+(16*devices) */ 0x00, /* u8 Bus 0 */ 0xf8, /* u8 Device 1, Function 0 */ 0x0000, /* u16 reserve IRQ for PCI */ @@ -13,28 +13,32 @@ const struct irq_routing_table intel_irq_routing_table = { 0x122e, /* Device ID */ 0x00000000, /* u32 miniport_data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x94, /* u8 checksum - mod 256 checksum must give zero */ + 0x37, /* u8 checksum - mod 256 checksum must give zero */ { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, 0x00, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00}, {0x00, 0x10, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00}, {0x01, 0xe8, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00}, - {0x02, 0x08, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x01, 0x00}, - {0x02, 0x18, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x0a, 0x00}, - {0x02, 0x10, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x03, 0x00}, + {0x02, 0x08, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x06, 0x00}, + {0x02, 0x10, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x07, 0x00}, {0x01, 0xf8, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00}, - {0x03, 0x08, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x02, 0x00}, - {0x03, 0x10, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x05, 0x00}, - {0x03, 0x18, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x06, 0x00}, - {0x03, 0x20, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x0b, 0x00}, + {0x03, 0x08, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x05, 0x00}, + {0x00, 0x18, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00}, + {0x04, 0xe8, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00}, + {0x05, 0x08, {{0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}}, 0x03, 0x00}, + {0x05, 0x10, {{0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}}, 0x02, 0x00}, + {0x05, 0x18, {{0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}}, 0x01, 0x00}, + {0x04, 0xf8, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00}, + {0x06, 0x08, {{0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}}, 0x04, 0x00}, + {0x06, 0x10, {{0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}}, 0x09, 0x00}, {0x00, 0x20, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00}, {0x10, 0xe8, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00}, - {0x11, 0x08, {{0x63, 0xdcb8}, {0x63, 0xdcb8}, {0x63, 0xdcb8}, {0x63, 0xdcb8}}, 0x03, 0x00}, + {0x11, 0x08, {{0x63, 0xdcb8}, {0x63, 0xdcb8}, {0x63, 0xdcb8}, {0x63, 0xdcb8}}, 0x08, 0x00}, {0x10, 0xf8, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00}, - {0x12, 0x08, {{0x63, 0xdcb8}, {0x63, 0xdcb8}, {0x63, 0xdcb8}, {0x63, 0xdcb8}}, 0x04, 0x00}, + {0x12, 0x08, {{0x63, 0xdcb8}, {0x63, 0xdcb8}, {0x63, 0xdcb8}, {0x63, 0xdcb8}}, 0x07, 0x00}, {0x00, 0xf0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00}, - {0x04, 0x08, {{0x60, 0xdcb8}, {0x60, 0xdcb8}, {0x60, 0xdcb8}, {0x60, 0xdcb8}}, 0x07, 0x00}, - {0x04, 0x10, {{0x61, 0xdcb8}, {0x61, 0xdcb8}, {0x61, 0xdcb8}, {0x61, 0xdcb8}}, 0x08, 0x00}, - {0x04, 0x18, {{0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}}, 0x09, 0x00}, + {0x07, 0x08, {{0x60, 0xdcb8}, {0x60, 0xdcb8}, {0x60, 0xdcb8}, {0x60, 0xdcb8}}, 0x0a, 0x00}, + {0x07, 0x10, {{0x61, 0xdcb8}, {0x61, 0xdcb8}, {0x61, 0xdcb8}, {0x61, 0xdcb8}}, 0x0b, 0x00}, + {0x07, 0x18, {{0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}}, 0x0c, 0x00}, {0x00, 0xe8, {{0x60, 0xdcb8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00}, {0x00, 0xe9, {{0x00, 0xdef8}, {0x63, 0xdcb8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00}, {0x00, 0xea, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x62, 0xdcb8}, {0x00, 0xdef8}}, 0x00, 0x00}, diff --git a/src/mainboard/supermicro/p4dpe/mainboard.c b/src/mainboard/supermicro/p4dpe/mainboard.c index 22cb3adcdf..8fa71517b4 100644 --- a/src/mainboard/supermicro/p4dpe/mainboard.c +++ b/src/mainboard/supermicro/p4dpe/mainboard.c @@ -18,10 +18,6 @@ #include -#define SMBUS_MEM_DEVICE_0 (0xa << 3) -extern int rdram_chips; /* number of ram chips on the rimms */ - - unsigned long initial_apicid[MAX_CPUS] = { 0, 6, 1, 7 @@ -31,8 +27,8 @@ unsigned long initial_apicid[MAX_CPUS] = #define CPU_CLOCK_MULTIPLIER XEON_X17 #endif +#define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -#define MAINBOARD_POWER_OFF 2 #ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL #define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON @@ -44,11 +40,11 @@ static void set_power_on_after_power_fail(int setting) case MAINBOARD_POWER_ON: default: ich3_power_after_power_fail(1); - w832627hf_power_after_power_fail(POWER_ON); + w83627hf_power_after_power_fail(POWER_ON); break; case MAINBOARD_POWER_OFF: ich3_power_after_power_fail(0); - w832627hf_power_after_power_fail(POWER_OFF); + w83627hf_power_after_power_fail(POWER_OFF); break; } @@ -74,8 +70,11 @@ void mainboard_fixup(void) int cpu_clock_multiplier; int power_on_after_power_fail; int thermal_monitoring; + + w83627hf_power_led(LED_ON); ich3_enable_ioapic(); p64h2_enable_ioapic(); + p64h2_setup_pcibridge(); ich3_enable_serial_irqs(); ich3_enable_ide(1,1); ich3_rtc_init(); @@ -84,13 +83,15 @@ void mainboard_fixup(void) ich3_1e0_misc(); ich3_1f0_misc(); +#if 0 /* CPU clock option is not presently used */ cpu_clock_multiplier = CPU_CLOCK_MULTIPLIER; if(get_option(&cpu_clock_multiplier, "CPU_clock_speed")) cpu_clock_multiplier = CPU_CLOCK_MULTIPLIER; ich3_set_cpu_multiplier(cpu_clock_multiplier); +#endif power_on_after_power_fail = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - if(get_option(&power_on_after_power_fail, "power_on_after_power_fail")) + if(get_option(&power_on_after_power_fail, "power_on_after_fail")) power_on_after_power_fail = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; set_power_on_after_power_fail(power_on_after_power_fail); @@ -107,103 +108,3 @@ void hard_reset(void) ich3_hard_reset(); } -static void select_rdram_i2c(void) -{ - unsigned char byte; - w83627hf_enter_pnp(SIO_BASE); - byte = pnp_read_config(SIO_BASE, 0x2b); - byte |= 0x30; - pnp_write_config(SIO_BASE, byte, 0x2b); - pnp_set_logical_device(SIO_BASE, GPIO_PORT2_DEVICE); - pnp_set_enable(SIO_BASE, 1); - byte = pnp_read_config(SIO_BASE, 0xf0); - byte &= ~(1 << 3); - pnp_write_config(SIO_BASE, byte, 0xf0); - w83627hf_exit_pnp(SIO_BASE); -} - -#if 0 -void cache_ram_start(void) -{ - int error; - - error = 0; - /* displayinit MUST PRECEDE ALL PRINTK! */ - -#if 1 - displayinit(); -#endif - printk_info("Finding PCI configuration type.\n"); - pci_set_method(); - printk_info("Setting up smbus controller\n"); - smbus_setup(); - ich3_rtc_init(); - printk_info("Selecting rdram i2c bus\n"); - select_rdram_i2c(); - -#if 0 - display_smbus_spd(); -#endif - - init_memory(); - -#if 0 - { - unsigned long addr; - for(addr = 0; addr < 0x20000000; addr += 0x02000000) { - ram_fill(addr, addr + 0x400); - } - /* Do some dummy writes to flush a write cache, in the - * processor. - */ - ram_fill(0xc0000000, 0xc0000400); - for(addr = 0; addr < 0x20000000; addr += 0x02000000) { - ram_verify(addr, addr + 0x400, 1); - } - } -#endif -#if 1 - printk_debug("starting ramcheck\n"); - error |= ramcheck(0x00000000, 0x00080000, 40); - error |= ramcheck(0x02000000, 0x02080000, 40); - error |= ramcheck(0x04000000, 0x04080000, 40); - error |= ramcheck(0x06000000, 0x06080000, 40); - error |= ramcheck(0x08000000, 0x08080000, 40); - error |= ramcheck(0x0a000000, 0x0a080000, 40); - error |= ramcheck(0x0c000000, 0x0c080000, 40); - error |= ramcheck(0x0e000000, 0x0e080000, 40); - error |= ramcheck(0x1a000000, 0x1a080000, 40); -#if 0 - error |= ramcheck(0x10000000, 0x10080000, 20); - error |= ramcheck(0x12000000, 0x12080000, 20); - error |= ramcheck(0x14000000, 0x14080000, 20); - error |= ramcheck(0x16000000, 0x16080000, 20); - error |= ramcheck(0x18000000, 0x18080000, 20); - error |= ramcheck(0x1a000000, 0x1a080000, 20); - error |= ramcheck(0x1c000000, 0x1c080000, 20); - error |= ramcheck(0x1e000000, 0x1e080000, 20); -#endif -#endif -#if 0 - error |= ramcheck(0x00000000, 0x00080000, 20); -#endif -#if 0 - display_rdram_regs(rdram_chips ); -#endif -#if 0 - display_mch_regs(); -#endif - if (error) { - printk_err("Something isn't working!!!\n"); - while(1); - } else { - printk_info("Leaving cacheram...\n"); - } - -} - -#endif - - - - diff --git a/src/mainboard/supermicro/p4dpe/mptable.c b/src/mainboard/supermicro/p4dpe/mptable.c index 6a7b87d7c6..14fad6f40e 100644 --- a/src/mainboard/supermicro/p4dpe/mptable.c +++ b/src/mainboard/supermicro/p4dpe/mptable.c @@ -1,5 +1,3 @@ -/* generatred by MPTable, version 2.0.15*/ -/* as modified by RGM for LinuxBIOS */ #include #include #include @@ -8,32 +6,31 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) { - static const char sig[4] = "PCMP"; - static const char oem[8] = "LNXI "; - static const char productid[12] = "P4DPE "; - struct mp_config_table *mc; + static const char sig[4] = "PCMP"; + static const char oem[8] = "LNXI "; + static const char productid[12] = "P4DPE "; + struct mp_config_table *mc; - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - memset(mc, 0, sizeof(*mc)); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); - memcpy(mc->mpc_signature, sig, sizeof(sig)); - mc->mpc_length = sizeof(*mc); /* initially just the header */ - mc->mpc_spec = 0x04; - mc->mpc_checksum = 0; /* not yet computed */ - memcpy(mc->mpc_oem, oem, sizeof(oem)); - memcpy(mc->mpc_productid, productid, sizeof(productid)); - mc->mpc_oemptr = 0; - mc->mpc_oemsize = 0; - mc->mpc_entry_count = 0; /* No entries yet... */ - mc->mpc_lapic = LAPIC_ADDR; - mc->mpe_length = 0; - mc->mpe_checksum = 0; - mc->reserved = 0; + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; - smp_write_processors(mc, processor_map); + smp_write_processors(mc, processor_map); - -/*Bus: Bus ID Type*/ + /*Bus: Bus ID Type*/ smp_write_bus(mc, 0, "PCI "); smp_write_bus(mc, 1, "PCI "); smp_write_bus(mc, 2, "PCI "); @@ -43,7 +40,10 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) smp_write_bus(mc, 6, "PCI "); smp_write_bus(mc, 7, "PCI "); smp_write_bus(mc, 8, "ISA "); -/*I/O APICs: APIC ID Version State Address*/ + + /* FIXME better IOAPIC handling */ + + /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 2, 0x20, 0xfec00000); { struct pci_dev *dev; @@ -60,51 +60,99 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) base &= PCI_BASE_ADDRESS_MEM_MASK; smp_write_ioapic(mc, 4, 0x20, base); } - dev = pci_find_slot(4, PCI_DEVFN(0x1e,0)); - if (dev) { - pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base); - base &= PCI_BASE_ADDRESS_MEM_MASK; - smp_write_ioapic(mc, 5, 0x20, base); - } - dev = pci_find_slot(4, PCI_DEVFN(0x1c,0)); - if (dev) { - pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base); - base &= PCI_BASE_ADDRESS_MEM_MASK; - smp_write_ioapic(mc, 8, 0x20, base); - } + dev = pci_find_slot(4, PCI_DEVFN(0x1e,0)); + if (dev) { + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 5, 0x20, base); + } + dev = pci_find_slot(4, PCI_DEVFN(0x1c,0)); + if (dev) { + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 8, 0x20, base); + } } -/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# -*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x0, 0x2, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x1, 0x2, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x0, 0x2, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x3, 0x2, 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x4, 0x2, 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x5, 0x2, 0x5); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x6, 0x2, 0x6); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x7, 0x2, 0x7); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x8, 0x2, 0x8); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x9, 0x2, 0x9); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0xc, 0x2, 0xc); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0xd, 0x2, 0xd); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0xe, 0x2, 0xe); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0xf, 0x2, 0xf); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x4, 0x4, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x8, 0x3, 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x9, 0x3, 0x5); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x7, 0x4, 0x2, 0x10); -/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x0, MP_APIC_ALL, 0x1); + + /* ISA backward compatibility interrupts */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + 0x08, 0x00, 0x02, 0x00); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + 0x08, 0x01, 0x02, 0x01); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + 0x08, 0x00, 0x02, 0x02); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + 0x08, 0x03, 0x02, 0x03); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + 0x08, 0x04, 0x02, 0x04); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x76, 0x02, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + 0x08, 0x06, 0x02, 0x06); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + 0x08, 0x07, 0x02, 0x07); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + 0x08, 0x08, 0x02, 0x08); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + 0x08, 0x09, 0x02, 0x09); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + 0x08, 0x0c, 0x02, 0x0c); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + 0x08, 0x0d, 0x02, 0x0d); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + 0x08, 0x0e, 0x02, 0x0e); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + 0x08, 0x0f, 0x02, 0x0f); + + /* Standard local interrupt assignments */ + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + 0x08, 0x00, MP_APIC_ALL, 0x00); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + 0x08, 0x00, MP_APIC_ALL, 0x01); + + /* Onboard ich3 southbridge (usb controller) */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, (0x1d<<2)|1, 0x02, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, (0x1d<<2)|0, 0x02, 0x10); + + /* Onboard 82559 Ethernet */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x07, (0x2<<2)|0, 0x02, 0x11); + /* Onboard ATI Video */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x07, (0x1<<2)|0, 0x02, 0x10); + + /* Slot 1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x02, (1<<2)|0, 0x04, 0x00); + /* Slot 2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x03, (1<<2)|0, 0x03, 0x00); + /* Slot 3 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x06, (1<<2)|0, 0x05, 0x00); + /* Slot 4 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x05, (1<<2)|0, 0x08, 0x00); + /* Slot 5 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x05, (2<<2)|0, 0x08, 0x04); + /* Slot 6 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x05, (3<<2)|0, 0x08, 0x08); + + /* Onboard Gigabit Intel NIC */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x07, (3<<2)|0, 0x02, 0x12); + /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); - printk_debug("Wrote the mp table end at: %p - %p -", + printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); } diff --git a/src/mainboard/supermicro/p4dpr/Config b/src/mainboard/supermicro/p4dpr/Config index afc060c59d..97ed6507ab 100644 --- a/src/mainboard/supermicro/p4dpr/Config +++ b/src/mainboard/supermicro/p4dpr/Config @@ -11,11 +11,6 @@ mainboardinit cpu/i386/entry32.inc ldscript cpu/i386/entry16.lds ldscript cpu/i386/entry32.lds -## -## Test for logical cpu thats not BSP -## -mainboardinit cpu/i786/logical_cpu.inc USE_FALLBACK_IMAGE - ## ## Build our reset vector (This is where linuxBIOS is entered) ## @@ -30,24 +25,18 @@ ldscript cpu/i386/reset32.lds USE_NORMAL_IMAGE mainboardinit arch/i386/lib/id.inc ldscript arch/i386/lib/id.lds -## -## Startup code for secondary CPUS -## -mainboardinit arch/i386/smp/secondary.inc - ## This is the early phase of linuxBIOS startup ## Things are delicate and we test to see if we should ## failover to another image. -mainboardinit northbridge/intel/82860/reset_test.inc +mainboardinit northbridge/intel/E7500/reset_test.inc mainboardinit arch/i386/lib/noop_failover.inc USE_NORMAL_IMAGE -mainboardinit southbridge/intel/82801/cmos_failover.inc USE_FALLBACK_IMAGE +mainboardinit southbridge/intel/82801ca/cmos_failover.inc USE_FALLBACK_IMAGE ldscript arch/i386/lib/failover.lds USE_FALLBACK_IMAGE ### ### O.k. We aren't just an intermediary anymore! ### - ## ## Setup our mtrrs ## @@ -59,24 +48,29 @@ mainboardinit cpu/i786/earlymtrr.inc mainboardinit superio/winbond/w83627hf/setup_serial.inc mainboardinit pc80/serial.inc mainboardinit arch/i386/lib/console.inc +mainboardinit southbridge/intel/82801ca/watchdog_disable.inc ## -## Switch temporarily into C code to setup RAM +## Reset pci clock for hardware bug work around ## -#mainboardinit cpu/i786/cache_ram_init.inc -## mainboardinit cpu/i786/cache_ram_test.inc -#mainboardinit cpu/i786/cache_ram_start.inc -#mainboardinit cpu/i786/cache_ram_fini.inc -#ldscript cpu/i786/cache_ram.lds +mainboardinit southbridge/intel/82801ca/smbus.inc +mainboardinit southbridge/intel/82801ca/smbus_write_block.inc +mainboardinit mainboard/supermicro/p4dpr/pci_clk_reset.inc -mainboardinit ram/ramtest.inc -option RAMTEST=1 -mainboardinit ram/dump_northbridge.inc +## +## Smbus functions +## +mainboardinit southbridge/intel/82801ca/smbus_read_byte.inc +#mainboardinit southbridge/intel/82801ca/smbus_read_block.inc +#mainboardinit southbridge/intel/82801ca/smbus_print_block.inc +mainboardinit mainboard/supermicro/p4dpr/select_i2c_spd.inc ## ## Setup RAM ## -#mainboardinit southbridge/intel/82801/smbus.inc +mainboardinit ram/spotcheck.inc +#mainboardinit ram/dump_northbridge.inc +#mainboardinit sdram/generic_dump_smbus.inc #mainboardinit sdram/generic_dump_spd.inc mainboardinit mainboard/supermicro/p4dpr/mainboard_raminit.inc @@ -86,7 +80,7 @@ mainboardinit mainboard/supermicro/p4dpr/mainboard_raminit.inc northbridge intel/E7500 southbridge intel/82801ca southbridge intel/82870 -nsuperio winbond/w83627hf com1={1} com2={1} floppy=1 lpt=1 keyboard=1 +nsuperio winbond/w83627hf com1={1} com2={1} floppy=1 lpt=1 keyboard=1 hwmonitor=1 dir /src/pc80 dir /src/superio/winbond/w83627hf dir /src/ram/ @@ -98,7 +92,7 @@ cpu i786 ## Build the objects we have code for in this directory. ## object mainboard.o -object mtrr_values.o +object devices.o object mptable.o HAVE_MP_TABLE object irq_tables.o HAVE_PIRQ_TABLE @@ -114,6 +108,7 @@ object irq_tables.o HAVE_PIRQ_TABLE option SMBUS_MEM_DEVICE_START=(0xa << 3) option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +3) option SMBUS_MEM_DEVICE_INC=1 +option SMBUS_MEM_CHANNEL_OFF=4 ## ## Customize our winbond superio chip for this motherboard @@ -129,7 +124,14 @@ option HAVE_FALLBACK_BOOT=1 ## ## Build code for using cache as RAM ## -option USE_CACHE_RAM=1 +#option USE_CACHE_RAM=0 + +## +## Delay timer options +## +option CONFIG_UDELAY_TSC=1 +option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + ## ## Build code to reset the motherboard from linuxBIOS @@ -182,22 +184,6 @@ option IOAPIC=1 ## nooption MEMORY_HOLE -## -## Don't do a generic MTRR setup -## Instead use values from the fixed_mtrr_values array -## -option HAVE_MTRR_TABLE=1 - -## -## Enable both fixed and variable MTRRS -## When we setup MTRRs in mtrr.c -## -## We must setup the fixed mtrrs or we confuse SMP secondary -## processor identification -## -option ENABLE_FIXED_AND_VARIABLE_MTRRS=1 - - ## ## Figure out which type of linuxBIOS image to build ## If we aren't a fallback image we must be a normal image @@ -240,6 +226,9 @@ option HEAP_SIZE=0x2000 option MAINBOARD_PART_NUMBER=P4DPR option MAINBOARD_VENDOR=Supermicro +option UPDATE_MICROCODE=1 +option CPU_FIXUP=1 + ## ## Only use the option table in a normal image ## diff --git a/src/mainboard/supermicro/p4dpr/mainboard.c b/src/mainboard/supermicro/p4dpr/mainboard.c index 22cb3adcdf..8fa71517b4 100644 --- a/src/mainboard/supermicro/p4dpr/mainboard.c +++ b/src/mainboard/supermicro/p4dpr/mainboard.c @@ -18,10 +18,6 @@ #include -#define SMBUS_MEM_DEVICE_0 (0xa << 3) -extern int rdram_chips; /* number of ram chips on the rimms */ - - unsigned long initial_apicid[MAX_CPUS] = { 0, 6, 1, 7 @@ -31,8 +27,8 @@ unsigned long initial_apicid[MAX_CPUS] = #define CPU_CLOCK_MULTIPLIER XEON_X17 #endif +#define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -#define MAINBOARD_POWER_OFF 2 #ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL #define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON @@ -44,11 +40,11 @@ static void set_power_on_after_power_fail(int setting) case MAINBOARD_POWER_ON: default: ich3_power_after_power_fail(1); - w832627hf_power_after_power_fail(POWER_ON); + w83627hf_power_after_power_fail(POWER_ON); break; case MAINBOARD_POWER_OFF: ich3_power_after_power_fail(0); - w832627hf_power_after_power_fail(POWER_OFF); + w83627hf_power_after_power_fail(POWER_OFF); break; } @@ -74,8 +70,11 @@ void mainboard_fixup(void) int cpu_clock_multiplier; int power_on_after_power_fail; int thermal_monitoring; + + w83627hf_power_led(LED_ON); ich3_enable_ioapic(); p64h2_enable_ioapic(); + p64h2_setup_pcibridge(); ich3_enable_serial_irqs(); ich3_enable_ide(1,1); ich3_rtc_init(); @@ -84,13 +83,15 @@ void mainboard_fixup(void) ich3_1e0_misc(); ich3_1f0_misc(); +#if 0 /* CPU clock option is not presently used */ cpu_clock_multiplier = CPU_CLOCK_MULTIPLIER; if(get_option(&cpu_clock_multiplier, "CPU_clock_speed")) cpu_clock_multiplier = CPU_CLOCK_MULTIPLIER; ich3_set_cpu_multiplier(cpu_clock_multiplier); +#endif power_on_after_power_fail = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - if(get_option(&power_on_after_power_fail, "power_on_after_power_fail")) + if(get_option(&power_on_after_power_fail, "power_on_after_fail")) power_on_after_power_fail = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; set_power_on_after_power_fail(power_on_after_power_fail); @@ -107,103 +108,3 @@ void hard_reset(void) ich3_hard_reset(); } -static void select_rdram_i2c(void) -{ - unsigned char byte; - w83627hf_enter_pnp(SIO_BASE); - byte = pnp_read_config(SIO_BASE, 0x2b); - byte |= 0x30; - pnp_write_config(SIO_BASE, byte, 0x2b); - pnp_set_logical_device(SIO_BASE, GPIO_PORT2_DEVICE); - pnp_set_enable(SIO_BASE, 1); - byte = pnp_read_config(SIO_BASE, 0xf0); - byte &= ~(1 << 3); - pnp_write_config(SIO_BASE, byte, 0xf0); - w83627hf_exit_pnp(SIO_BASE); -} - -#if 0 -void cache_ram_start(void) -{ - int error; - - error = 0; - /* displayinit MUST PRECEDE ALL PRINTK! */ - -#if 1 - displayinit(); -#endif - printk_info("Finding PCI configuration type.\n"); - pci_set_method(); - printk_info("Setting up smbus controller\n"); - smbus_setup(); - ich3_rtc_init(); - printk_info("Selecting rdram i2c bus\n"); - select_rdram_i2c(); - -#if 0 - display_smbus_spd(); -#endif - - init_memory(); - -#if 0 - { - unsigned long addr; - for(addr = 0; addr < 0x20000000; addr += 0x02000000) { - ram_fill(addr, addr + 0x400); - } - /* Do some dummy writes to flush a write cache, in the - * processor. - */ - ram_fill(0xc0000000, 0xc0000400); - for(addr = 0; addr < 0x20000000; addr += 0x02000000) { - ram_verify(addr, addr + 0x400, 1); - } - } -#endif -#if 1 - printk_debug("starting ramcheck\n"); - error |= ramcheck(0x00000000, 0x00080000, 40); - error |= ramcheck(0x02000000, 0x02080000, 40); - error |= ramcheck(0x04000000, 0x04080000, 40); - error |= ramcheck(0x06000000, 0x06080000, 40); - error |= ramcheck(0x08000000, 0x08080000, 40); - error |= ramcheck(0x0a000000, 0x0a080000, 40); - error |= ramcheck(0x0c000000, 0x0c080000, 40); - error |= ramcheck(0x0e000000, 0x0e080000, 40); - error |= ramcheck(0x1a000000, 0x1a080000, 40); -#if 0 - error |= ramcheck(0x10000000, 0x10080000, 20); - error |= ramcheck(0x12000000, 0x12080000, 20); - error |= ramcheck(0x14000000, 0x14080000, 20); - error |= ramcheck(0x16000000, 0x16080000, 20); - error |= ramcheck(0x18000000, 0x18080000, 20); - error |= ramcheck(0x1a000000, 0x1a080000, 20); - error |= ramcheck(0x1c000000, 0x1c080000, 20); - error |= ramcheck(0x1e000000, 0x1e080000, 20); -#endif -#endif -#if 0 - error |= ramcheck(0x00000000, 0x00080000, 20); -#endif -#if 0 - display_rdram_regs(rdram_chips ); -#endif -#if 0 - display_mch_regs(); -#endif - if (error) { - printk_err("Something isn't working!!!\n"); - while(1); - } else { - printk_info("Leaving cacheram...\n"); - } - -} - -#endif - - - - diff --git a/src/mainboard/supermicro/p4dpr/mptable.c b/src/mainboard/supermicro/p4dpr/mptable.c index 25fd4b7a43..8f61098948 100644 --- a/src/mainboard/supermicro/p4dpr/mptable.c +++ b/src/mainboard/supermicro/p4dpr/mptable.c @@ -1,10 +1,11 @@ #include #include #include +#include +#include void *smp_write_config_table(void *v, unsigned long * processor_map) { - int ioapicid = 0; static const char sig[4] = "PCMP"; static const char oem[8] = "LNXI "; static const char productid[12] = "P4DPR "; @@ -27,16 +28,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) mc->mpe_checksum = 0; mc->reserved = 0; -#if 1 - smp_write_processor(mc, 0x00, 0x14, CPU_BOOTPROCESSOR | CPU_ENABLED, - 0x00000f24, 0x3febfbff); - smp_write_processor(mc, 0x06, 0x14, CPU_ENABLED, 0x00000f24, 0x3febfbff); - smp_write_processor(mc, 0x01, 0x14, CPU_ENABLED, 0x00000f24, 0x3febfbff); - smp_write_processor(mc, 0x07, 0x14, CPU_ENABLED, 0x00000f24, 0x3febfbff); -#else smp_write_processors(mc, processor_map); -#endif - ioapicid = 2; smp_write_bus(mc, 0, "PCI "); smp_write_bus(mc, 1, "PCI "); @@ -44,17 +36,30 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) smp_write_bus(mc, 3, "PCI "); smp_write_bus(mc, 4, "PCI "); smp_write_bus(mc, 5, "ISA "); + + /* FIXME better IOAPIC handling */ -#if 1 smp_write_ioapic(mc, 2, 0x20, 0xfec00000); - smp_write_ioapic(mc, 3, 0x20, 0xfec80000); - smp_write_ioapic(mc, 4, 0x20, 0xfec80400); -#else - smp_write_ioapic(mc, 4, 0x20, 0xfec00000); - smp_write_ioapic(mc, 5, 0x20, 0xfec80000); - smp_write_ioapic(mc, 8, 0x20, 0xfec80400); -#endif + { + struct pci_dev *dev; + uint32_t base; + /* 1:1e.0 */ + dev = pci_find_slot(1, PCI_DEVFN(0x1e,0)); + if (dev) { + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 3, 0x20, base); + } + /* 1:1c.0 */ + dev = pci_find_slot(1, PCI_DEVFN(0x1c,0)); + if (dev) { + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 4, 0x20, base); + } + } + /* ISA backward compatibility interrupts */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x05, 0x00, 0x02, 0x00); @@ -76,108 +81,49 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) 0x05, 0x08, 0x02, 0x08); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x05, 0x09, 0x02, 0x09); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x75, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x74, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x04, 0x08, 0x02, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x05, 0x0d, 0x02, 0x0d); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x05, 0x0e, 0x02, 0x0e); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x05, 0x0f, 0x02, 0x0f); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x03, 0x04, 0x03, 0x00); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x03, 0x10, 0x03, 0x07); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x04, 0x04, 0x02, 0x10); - smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - 0x05, 0x00, MP_APIC_ALL, 0x00); - smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - 0x05, 0x00, MP_APIC_ALL, 0x01); - - -#if 0 - /* Onboard ich2 soutbhridge */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, (0x1f << 2)|3, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, (0x1f << 2)|2, 0x02, 0x17); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, (0x1f << 2)|1, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, (0x1f << 2)|0, 0x02, 0x10); - - /* agp slot */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x01, 0x00, 0x02, 0x16); - - /* Onboard PCI NIC */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x04, (4 <<2)|0, 0x02, 0x10); - - /* Four standard PCI slots */ - /* Slot 1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x04, (7 <<2)|0, 0x02, 0x10); - /* Slot 2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x04, (1 <<2)|0, 0x02, 0x11); - /* Slot 3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x04, (2 <<2)|0, 0x02, 0x12); - /* Slot 4 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x04, (3 <<2)|0, 0x02, 0x13); - - /* Two 64 bit PCI slots */ - /* Slot 1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x03, (1 <<2)|0, 0x02, 0x12); - /* Slot 2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x03, (2 <<2)|0, 0x02, 0x12); - - /* Two SCSI */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x03, (4 <<2)|0, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x03, (4 <<2)|1, 0x02, 0x12); - - /* ISA backward compatibility interrupts */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x05, 0x00, 0x02, 0x00); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x05, 0x01, 0x02, 0x01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x05, 0x00, 0x02, 0x02); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x05, 0x03, 0x02, 0x03); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x05, 0x04, 0x02, 0x04); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x05, 0x06, 0x02, 0x06); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x05, 0x07, 0x02, 0x07); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - 0x05, 0x08, 0x02, 0x08); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x05, 0x0d, 0x02, 0x0d); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x05, 0x0e, 0x02, 0x0e); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x05, 0x0f, 0x02, 0x0f); /* Standard local interrupt assignments */ - smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x00, 0x00, MP_APIC_ALL, 0x00); - smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x00, 0x00, MP_APIC_ALL, 0x01); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + 0x05, 0x00, MP_APIC_ALL, 0x00); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + 0x05, 0x00, MP_APIC_ALL, 0x01); + + /* Onboard ich3 southbridge (usb controller) */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, (0x1d<<2)|1, 0x02, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, (0x1d<<2)|0, 0x02, 0x10); + + /* Onboard 82559 Ethernet */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x04, (0x2<<2)|0, 0x02, 0x11); + /* Onboard ATI Video */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x04, (0x1<<2)|0, 0x02, 0x10); + +#if 1 + /* Slot 1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x02, (1<<2)|0, 0x04, 0x00); #endif - + +#if 1 + /* Slot 2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x03, (1<<2)|0, 0x03, 0x00); + + /* Onboard Gigabit Intel NIC */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x03, (4<<2)|0, 0x03, 0x07); +#endif + + /* There is no extension information... */ /* Compute the checksums */