From 1e25b32b81fe9d1799c3aa32719e27f0ea65c4a1 Mon Sep 17 00:00:00 2001 From: Bernie Thompson Date: Fri, 13 Dec 2013 15:30:57 -0800 Subject: [PATCH] Rambi: Enable 32k SUSCLK signal The SoC needs to provide a 32k clock signal SUSCLK for some modems to work properly, so this enables the signal. BUG=chrome-os-partner:24425 TEST=Manual, check SUSCLK pin with a scope. Change-Id: I81fcc5a1fd27f4e1261fc761ea6eb017649acfa2 Reviewed-on: https://chromium-review.googlesource.com/180101 Reviewed-by: Aaron Durbin Commit-Queue: Bernie Thompson Tested-by: Bernie Thompson --- src/mainboard/google/rambi/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index 6e6efe6f11..3407bf31ef 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -169,7 +169,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { GPIO_FUNC6, /* S502 - TOUCH_INT# - INT */ GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ - GPIO_NC, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ GPIO_NC, /* S508 - NC */