From 1e1e99d723c365d141201a9c396ba66bbbdcc208 Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Fri, 30 Jan 2026 18:25:07 +0100
Subject: [PATCH] soc/intel/pantherlake: Include FSP API header globally
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As discussed under CB:88768, building for PantherLake targets fails due
to odd race-condition:
```
src/include/stdint.h:66:9: error: "INT32_MAX" redefined [-Werror]
   66 | #define INT32_MAX  ((int32_t)0x7FFFFFFF)
      |         ^~~~~~~~~
[...]
  129 |   #define INT32_MAX                       (0x7FFFFFFF)
      |           ^~~~~~~~~
cc1: all warnings being treated as errors
make: *** Waiting for unfinished jobs....
```

Board maintainers shouldn't need to include the FSP API header in their
ports, adding this header globally to meminit.h resolves the
race-condition and allows the build to finish.

Change-Id: Id7656d476ca6db78ea74629ef37a20323362997a
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91023
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/mainboard/google/fatcat/romstage.c          | 1 -
 src/mainboard/intel/ptlrvp/romstage.c           | 1 -
 src/soc/intel/pantherlake/include/soc/meminit.h | 1 +
 3 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mainboard/google/fatcat/romstage.c b/src/mainboard/google/fatcat/romstage.c
index 4e3c5b764a..9cece34bf6 100644
--- a/src/mainboard/google/fatcat/romstage.c
+++ b/src/mainboard/google/fatcat/romstage.c
@@ -4,7 +4,6 @@
 #include <baseboard/variants.h>
 #include <bootmode.h>
 #include <ec/google/chromeec/ec.h>
-#include <fsp/api.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
 #include <string.h>
diff --git a/src/mainboard/intel/ptlrvp/romstage.c b/src/mainboard/intel/ptlrvp/romstage.c
index 1172f006cb..e228f3a5bd 100644
--- a/src/mainboard/intel/ptlrvp/romstage.c
+++ b/src/mainboard/intel/ptlrvp/romstage.c
@@ -2,7 +2,6 @@
 
 #include <baseboard/variants.h>
 #include <ec/intel/board_id.h>
-#include <fsp/api.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
 #include <string.h>
diff --git a/src/soc/intel/pantherlake/include/soc/meminit.h b/src/soc/intel/pantherlake/include/soc/meminit.h
index 63404f8c17..d9506500ef 100644
--- a/src/soc/intel/pantherlake/include/soc/meminit.h
+++ b/src/soc/intel/pantherlake/include/soc/meminit.h
@@ -3,6 +3,7 @@
 #ifndef _SOC_PANTHERLAKE_MEMINIT_H_
 #define _SOC_PANTHERLAKE_MEMINIT_H_
 
+#include <fsp/api.h>
 #include <fsp/soc_binding.h>
 #include <intelblocks/meminit.h>
 #include <types.h>