From 1d912302e9dcc9c6ba69e15434bb1841e1196208 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Wed, 9 Apr 2014 16:02:52 -0700 Subject: [PATCH] tegra124: Use correct mask for APB bus width It worked earlier since the APB and AHB bus widths occupy the same bits in their respective registers. BUG=none BRANCH=none TEST=tested on Nyan Signed-off-by: David Hendricks Change-Id: I9b18c648c60dcc4ad62ca1f514d253f8cccaeee7 Reviewed-on: https://chromium-review.googlesource.com/194478 Tested-by: David Hendricks Reviewed-by: Gabe Black Commit-Queue: David Hendricks --- src/soc/nvidia/tegra124/spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 77f017d0fd..f6d2422cbe 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -453,7 +453,7 @@ static void setup_dma_params(struct tegra_spi_channel *spi, { /* APB bus width = 8-bits, address wrap for each word */ clrbits_le32(&dma->regs->apb_seq, - AHB_BUS_WIDTH_MASK << AHB_BUS_WIDTH_SHIFT); + APB_BUS_WIDTH_MASK << APB_BUS_WIDTH_SHIFT); /* AHB 1 word burst, bus width = 32 bits (fixed in hardware), * no address wrapping */ clrsetbits_le32(&dma->regs->ahb_seq,