From 1c0186f28064415b0d491d3f59a71118ac37909f Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Thu, 4 Sep 2025 12:13:25 -0700
Subject: [PATCH] soc/intel/common/block/cnvi: Add CNVi chip configuration
 support

This commit introduces a new configuration structure for the
Connectivity Integration (CNVi) block in Intel SoCs.

The added soc_intel_common_block_cnvi_config structure, located in
chip.h, defines a wake pin that specifies the ACPI Power Resources for
Wake (_PRW), enabling wake-up capabilities from sleep states.

This enhancement provides a structured way to handle CNVi
configurations, which is crucial for managing device power states and
ensuring proper wake functionalities as defined by ACPI standards.

Change-Id: Ide6dea04cb089d73fe6aad9fb91044f9eb43edc6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
---
 src/soc/intel/common/block/cnvi/chip.h | 19 +++++++++++
 src/soc/intel/common/block/cnvi/cnvi.c | 44 ++++++++++++++++++++++++++
 2 files changed, 63 insertions(+)
 create mode 100644 src/soc/intel/common/block/cnvi/chip.h

diff --git a/src/soc/intel/common/block/cnvi/chip.h b/src/soc/intel/common/block/cnvi/chip.h
new file mode 100644
index 0000000000..7f50ffb946
--- /dev/null
+++ b/src/soc/intel/common/block/cnvi/chip.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_INTEL_COMMON_BLOCK_CNVI_H_
+#define _SOC_INTEL_COMMON_BLOCK_CNVI_H_
+
+/**
+ * struct soc_intel_common_block_cnvi_config - Configuration structure for CNVi
+ * @wake: Specifies the wake pin used for ACPI Power Resources for Wake (_PRW).
+ *
+ * This structure holds the configuration data required for setting up the
+ * Connectivity Integration (CNVi) block in Intel SoCs. The wake pin is
+ * utilized to enable wake-up capabilities from sleep states as defined
+ * by the ACPI specification.
+ */
+struct soc_intel_common_block_cnvi_config {
+	unsigned int wake;
+};
+
+#endif /* SOC_INTEL_COMMON_BLOCK_CNVI_H_ */
diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index 6ca91b1190..9314c989ed 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -10,6 +10,8 @@
 #include <soc/cnvi.h>
 #include <soc/pcr_ids.h>
 
+#include "chip.h"
+
 static const char *cnvi_wifi_acpi_name(const struct device *dev)
 {
 	return "CNVW";
@@ -871,3 +873,45 @@ static const struct pci_driver pch_cnvi_bt __pci_driver = {
 	.vendor			= PCI_VID_INTEL,
 	.devices		= bt_pci_device_ids,
 };
+
+static const char *cnvi_acpi_name(const struct device *dev)
+{
+	const struct device *parent = dev->upstream->dev;
+	return parent->ops->acpi_name(parent);
+}
+
+static void cnvi_acpi_fill_ssdt(const struct device *dev)
+{
+	const struct device *parent = dev->upstream->dev;
+	const char *scope = acpi_device_path(parent);
+	acpigen_write_scope(scope);
+
+	const struct soc_intel_common_block_cnvi_config *config = dev->chip_info;
+	if (config) {
+/*		Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
+ *		{
+ *		    $(config->wake),
+ *		    0x03
+ *		})
+ */
+		acpigen_write_PRW(config->wake, ACPI_S3);
+	}
+	acpigen_write_scope_end();
+}
+
+static struct device_operations cnvi_ops = {
+	.read_resources = noop_read_resources,
+	.set_resources = noop_set_resources,
+	.acpi_fill_ssdt = cnvi_acpi_fill_ssdt,
+	.acpi_name = cnvi_acpi_name,
+};
+
+static void cnvi_enable_dev(struct device *dev)
+{
+	dev->ops = &cnvi_ops;
+}
+
+struct chip_operations soc_intel_common_block_cnvi_ops = {
+	.name = "CNVi Device",
+	.enable_dev = cnvi_enable_dev,
+};