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armv7: Allow accessing ACTLR (Auxiliary Control Register).

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The ACTLR provides implementation defined configuration and control options for
the processor.

BUG=none
TEST=emerge-peach_pit chromeos-coreboot-peach_pit # success.
BRANCH=none

Change-Id: I74df1ed7887eb3f16a1b8297db998ec2f8b18311
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65107
Commit-Queue: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Hung-Te Lin 2013-08-08 11:07:40 +08:00 • committed by ChromeBot
commit 1b8ca4bbfb
1 changed files with 14 additions and 0 deletions
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14
src/arch/armv7/include/arch/cpu.h
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@ -66,6 +66,20 @@ inline static uint32_t read_mpidr(void)
return value;
}
/* read Auxiliary Control Register (ACTLR) */
inline static uint32_t read_actlr(void)
{
uint32_t val = 0;
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r"(val));
return val;
}
/* write Auxiliary Control Register (ACTLR) */
inline static void write_actlr(uint32_t val)
{
asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (val));
}
/* wait for interrupt. */
inline static void wfi(void)
{