From 1b80d71e4942310bd7e83c5565c6a06c30811821 Mon Sep 17 00:00:00 2001
From: Aaron Durbin <adurbin@chromium.org>
Date: Fri, 17 Jan 2014 14:15:44 -0600
Subject: [PATCH] baytrail: initialize rtc device

Add support for initializing the rtc device. Also
add RTC well loss events to the eventlog and properly
clear the event so it doesn't get added again.

BUG=None
BRANCH=baytrail
TEST=Built and booted. Tested battery loss. Eventlog
     has RTC event. In addition the rtc device can
     be properly probed in the kernel resulting in
     /sys/class/rtc/rtc0 being available.

Change-Id: I1ca608b069dc50db116d75963d5542a7f9b1811f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183051
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
---
 src/soc/intel/baytrail/elog.c         |  4 ++++
 src/soc/intel/baytrail/pmutil.c       |  4 ++--
 src/soc/intel/baytrail/southcluster.c | 25 +++++++++++++++++++++++++
 3 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c
index 8c6be9f319..f50d1301f3 100644
--- a/src/soc/intel/baytrail/elog.c
+++ b/src/soc/intel/baytrail/elog.c
@@ -42,6 +42,10 @@ static void log_power_and_resets(const struct chipset_power_state *ps)
 		elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
 	}
 
+	if (ps->gen_pmcon1 & RPS) {
+		elog_add_event(ELOG_TYPE_RTC_RESET);
+	}
+
 	if (ps->tco_sts & SECOND_TO_STS) {
 		elog_add_event(ELOG_TYPE_TCO_RESET);
 	}
diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c
index 5d37a1366d..aee37261be 100644
--- a/src/soc/intel/baytrail/pmutil.c
+++ b/src/soc/intel/baytrail/pmutil.c
@@ -358,7 +358,7 @@ void clear_pmc_status(void)
 	prsts = read32(PMC_BASE_ADDRESS + PRSTS);
 	gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
 
-	/* Clear the status bits. */
-	write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1);
+	/* Clear the status bits. The RPS field is cleared on a 0 write. */
+	write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1 & ~RPS);
 	write32(PMC_BASE_ADDRESS + PRSTS, prsts);
 }
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index a416115b8c..1ee5edc660 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -20,10 +20,12 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <cbmem.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <pc80/mc146818rtc.h>
 #include <romstage_handoff.h>
 
 #include <baytrail/iomap.h>
@@ -117,6 +119,27 @@ static void sc_read_resources(device_t dev)
 	sc_add_io_resources(dev);
 }
 
+static void sc_rtc_init(void)
+{
+	uint32_t gen_pmcon1;
+	int rtc_fail;
+	struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
+
+	if (ps != NULL) {
+		gen_pmcon1 = ps->gen_pmcon1;
+	} else {
+		gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
+	}
+
+	rtc_fail = !!(gen_pmcon1 & RPS);
+
+	if (rtc_fail) {
+		printk(BIOS_DEBUG, "RTC failure.\n");
+	}
+
+	rtc_init(rtc_fail);
+}
+
 static void sc_init(device_t dev)
 {
 	int i;
@@ -136,6 +159,8 @@ static void sc_init(device_t dev)
 
 	/* Route SCI to IRQ9 */
 	write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9);
+
+	sc_rtc_init();
 }
 
 /*