From 19fe81f08f5eff7377b0f8595a1763874f0aeec3 Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Fri, 13 Feb 2026 23:35:32 -0800 Subject: [PATCH] soc/intel/alderlake: Switch to common PMC lockdown driver Replace platform-specific lockdown.c with the common PMC lockdown driver introduced in the previous commit. Changes: - Remove src/soc/intel/alderlake/lockdown.c - Add PMC_FDIS_LOCK_REG define pointing to ST_PG_FDIS1 in soc/pmc.h - Enable SOC_INTEL_COMMON_FEATURE_PMC_LOCKDOWN in Kconfig - Update Makefile.mk to remove lockdown.c from build Alder Lake uses the ST_PG_FDIS1 register (0x1e20) for ST_FDIS_LOCK, which differs from newer platforms that use GEN_PMCON_B. This difference is handled through the PMC_FDIS_LOCK_REG define. Change-Id: Ic80aca618dcbe5a4fef54f4802e6f4ce6f4ebd44 Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/91205 Reviewed-by: Huang, Cliff Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/Kconfig | 1 + src/soc/intel/alderlake/Makefile.mk | 1 - src/soc/intel/alderlake/include/soc/pmc.h | 3 ++ src/soc/intel/alderlake/lockdown.c | 60 ----------------------- 4 files changed, 4 insertions(+), 61 deletions(-) delete mode 100644 src/soc/intel/alderlake/lockdown.c diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index a925cf09a0..9198377291 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -87,6 +87,7 @@ config SOC_INTEL_ALDERLAKE select SOC_INTEL_COMMON_FEATURE select SOC_INTEL_COMMON_FEATURE_ESPI select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN + select SOC_INTEL_COMMON_FEATURE_LOCKDOWN select SOC_INTEL_COMMON_FEATURE_PMUTIL select SOC_INTEL_COMMON_FEATURE_SMIHANDLER select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk index 45c374849d..cbfa1ebda5 100644 --- a/src/soc/intel/alderlake/Makefile.mk +++ b/src/soc/intel/alderlake/Makefile.mk @@ -25,7 +25,6 @@ ramstage-y += finalize.c ramstage-y += fsp_params.c ramstage-y += graphics.c ramstage-y += hsphy.c -ramstage-y += lockdown.c ramstage-y += p2sb.c ramstage-y += pcie_rp.c ramstage-y += pmc.c diff --git a/src/soc/intel/alderlake/include/soc/pmc.h b/src/soc/intel/alderlake/include/soc/pmc.h index 81a99e00ec..aa7df21bee 100644 --- a/src/soc/intel/alderlake/include/soc/pmc.h +++ b/src/soc/intel/alderlake/include/soc/pmc.h @@ -168,6 +168,9 @@ extern struct device_operations pmc_ops; #define ST_PG_FDIS1 0x1e20 #define ST_FDIS_LOCK (1 << 31) +/* PMC lockdown configuration register for ST_FDIS_LOCK */ +#define PMC_FDIS_LOCK_REG ST_PG_FDIS1 + #define SCIS_IRQ9 0 #define SCIS_IRQ10 1 #define SCIS_IRQ11 2 diff --git a/src/soc/intel/alderlake/lockdown.c b/src/soc/intel/alderlake/lockdown.c deleted file mode 100644 index 59fa065b3d..0000000000 --- a/src/soc/intel/alderlake/lockdown.c +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * This file is created based on Intel Alder Lake Processor PCH Datasheet - * Document number: 621483 - * Chapter number: 4 - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* PCR PSTH Control Register */ -#define PCR_PSTH_CTRLREG 0x1d00 -#define PSTH_CTRLREG_IOSFPTCGE (1 << 2) - -static void pmc_lockdown_cfg(int chipset_lockdown) -{ - uint8_t *pmcbase = pmc_mmio_regs(); - - /* PMSYNC */ - setbits32(pmcbase + PMSYNC_TPR_CFG, PCH2CPU_TPR_CFG_LOCK); - /* Lock down ABASE and sleep stretching policy */ - setbits32(pmcbase + GEN_PMCON_B, SLP_STR_POL_LOCK | ACPI_BASE_LOCK); - - if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) - setbits32(pmcbase + GEN_PMCON_B, SMI_LOCK); - - if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) { - setbits32(pmcbase + ST_PG_FDIS1, ST_FDIS_LOCK); - setbits32(pmcbase + SSML, SSML_SSL_EN); - setbits32(pmcbase + PM_CFG, PM_CFG_DBG_MODE_LOCK | - PM_CFG_XRAM_READ_DISABLE); - } - - /* Send PMC IPC to inform about both BIOS Reset and PCI enumeration done */ - pmc_send_bios_reset_pci_enum_done(); -} - -static void pch_lockdown_cfg(void) -{ - if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) - return; - - /* Enable IOSF Primary Trunk Clock Gating */ - pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE); -} - -void soc_lockdown_config(int chipset_lockdown) -{ - /* PMC lock down configuration */ - pmc_lockdown_cfg(chipset_lockdown); - /* PCH lock down configuration */ - pch_lockdown_cfg(); -}