From 18a986c5fe63a5e801e9cdd493a903d588312a0a Mon Sep 17 00:00:00 2001 From: Maximilian Brune Date: Tue, 26 Aug 2025 02:17:56 +0200 Subject: [PATCH] soc/amd/cmn/block/cpu/mca: Support MCA_SYND1 and MCA_SYND2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The number of MCAX register used inside an MCA BANK changed from phoenix onwards. Since phoenix all 16 MCAX register are used inside an MCA bank. According to spec: The MCA_SYND register stores a syndrome associated with the error logged in MCA_STATUS or MCA_DESTAT. The “syndrome” may include syndrome values associated with an error correcting code or other information about the error. The contents of this register are valid if MCA_STATUS[SYNDV] bit is set to 1 or MCA_DESTAT[SYNDV] bit is set to 1. source: AMD64 Architecture Programmers Manual Rev 3.42 Change-Id: I20a31776d4b031c810ef0dc6502c421ade6f4315 Signed-off-by: Maximilian Brune Reviewed-on: https://review.coreboot.org/c/coreboot/+/90640 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/amd/common/block/cpu/mca/mcax.c | 10 ++++++++-- src/soc/amd/common/block/cpu/mca/mcax_bert.c | 15 +++++++-------- .../amd/common/block/include/amdblocks/msr_zen.h | 5 +++++ 3 files changed, 20 insertions(+), 10 deletions(-) diff --git a/src/soc/amd/common/block/cpu/mca/mcax.c b/src/soc/amd/common/block/cpu/mca/mcax.c index 46c72f00a8..ad4f67e47d 100644 --- a/src/soc/amd/common/block/cpu/mca/mcax.c +++ b/src/soc/amd/common/block/cpu/mca/mcax.c @@ -20,14 +20,14 @@ bool mca_skip_check(void) /* Print the contents of the MCAX registers for a given bank */ void mca_print_error(unsigned int bank) { - msr_t msr; + msr_t msr, mca_status; printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", initial_lapicid(), bank, mca_get_bank_name(bank)); msr = rdmsr(MCAX_CTL_MSR(bank)); printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n", bank, msr.hi, msr.lo); - msr = rdmsr(MCAX_STATUS_MSR(bank)); + msr = mca_status = rdmsr(MCAX_STATUS_MSR(bank)); printk(BIOS_WARNING, " MC%u_STATUS = %08x_%08x\n", bank, msr.hi, msr.lo); msr = rdmsr(MCAX_ADDR_MSR(bank)); printk(BIOS_WARNING, " MC%u_ADDR = %08x_%08x\n", bank, msr.hi, msr.lo); @@ -51,6 +51,12 @@ void mca_print_error(unsigned int bank) printk(BIOS_WARNING, " MC%u_MISC3 = %08x_%08x\n", bank, msr.hi, msr.lo); msr = rdmsr(MCAX_MISC4_MSR(bank)); printk(BIOS_WARNING, " MC%u_MISC4 = %08x_%08x\n", bank, msr.hi, msr.lo); + if (mca_syndv(mca_status)) { + msr = rdmsr(MCAX_SYND1_MSR(bank)); + printk(BIOS_WARNING, " MC%u_SYND1 = %08x_%08x\n", bank, msr.hi, msr.lo); + msr = rdmsr(MCAX_SYND2_MSR(bank)); + printk(BIOS_WARNING, " MC%u_SYND2 = %08x_%08x\n", bank, msr.hi, msr.lo); + } msr = rdmsr(MCA_CTL_MASK_MSR(bank)); printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); } diff --git a/src/soc/amd/common/block/cpu/mca/mcax_bert.c b/src/soc/amd/common/block/cpu/mca/mcax_bert.c index af2bee407d..80ee534f45 100644 --- a/src/soc/amd/common/block/cpu/mca/mcax_bert.c +++ b/src/soc/amd/common/block/cpu/mca/mcax_bert.c @@ -10,10 +10,7 @@ #include #include "mca_common_defs.h" -/* MISC4 is the last used register in the MCAX banks of Picasso */ -#define MCAX_USED_REGISTERS_PER_BANK (MCAX_MISC4_OFFSET + 1) - -static inline size_t mca_report_size_reqd(void) +static inline size_t mca_report_size_reqd(int used_registers_per_bank) { size_t size; @@ -32,8 +29,8 @@ static inline size_t mca_report_size_reqd(void) size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 3); /* Context of CTL, STATUS, ADDR, MISC0, CONFIG, IPID, SYND, RESERVED, DESTAT, DEADDR, - MISC1, MISC2, MISC3, MISC4 */ - size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, MCAX_USED_REGISTERS_PER_BANK); + MISC1, MISC2, MISC3, MISC4, SYND0, SYND1 */ + size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, used_registers_per_bank); /* Context of CTL_MASK */ size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 1); @@ -57,7 +54,9 @@ void build_bert_mca_error(struct mca_bank_status *mci) cper_ia32x64_proc_error_info_t *chk; cper_ia32x64_context_t *ctx; - if (mca_report_size_reqd() > bert_storage_remaining()) + int used_registers_per_bank = mca_syndv(mci->sts) ? 16 : 14; + + if (mca_report_size_reqd(used_registers_per_bank) > bert_storage_remaining()) goto failed; status = bert_new_event(&CPER_SEC_PROC_GENERIC_GUID); @@ -80,7 +79,7 @@ void build_bert_mca_error(struct mca_bank_status *mci) if (!ctx) goto failed; ctx = cper_new_ia32x64_context_msr(status, x86_sec, MCAX_CTL_MSR(mci->bank), - MCAX_USED_REGISTERS_PER_BANK); + used_registers_per_bank); if (!ctx) goto failed; ctx = cper_new_ia32x64_context_msr(status, x86_sec, MCA_CTL_MASK_MSR(mci->bank), 1); diff --git a/src/soc/amd/common/block/include/amdblocks/msr_zen.h b/src/soc/amd/common/block/include/amdblocks/msr_zen.h index 0e2d2c8fec..cde4d7bdda 100644 --- a/src/soc/amd/common/block/include/amdblocks/msr_zen.h +++ b/src/soc/amd/common/block/include/amdblocks/msr_zen.h @@ -24,6 +24,9 @@ #define MCAX_MISC2_OFFSET 0xb #define MCAX_MISC3_OFFSET 0xc #define MCAX_MISC4_OFFSET 0xd +#define MCAX_SYND1_OFFSET 0xe +#define MCAX_SYND2_OFFSET 0xf + #define MCAX_MSR(bank, offset) (MCAX_MSR_BASE + (bank) * MCAX_BANK_SIZE + (offset)) #define MCAX_CTL_MSR(bank) MCAX_MSR(bank, MCAX_CTL_OFFSET) #define MCAX_STATUS_MSR(bank) MCAX_MSR(bank, MCAX_STATUS_OFFSET) @@ -38,6 +41,8 @@ #define MCAX_MISC2_MSR(bank) MCAX_MSR(bank, MCAX_MISC2_OFFSET) #define MCAX_MISC3_MSR(bank) MCAX_MSR(bank, MCAX_MISC3_OFFSET) #define MCAX_MISC4_MSR(bank) MCAX_MSR(bank, MCAX_MISC4_OFFSET) +#define MCAX_SYND1_MSR(bank) MCAX_MSR(bank, MCAX_SYND1_OFFSET) +#define MCAX_SYND2_MSR(bank) MCAX_MSR(bank, MCAX_SYND2_OFFSET) /* * The MCA CTL_MASK moved to a new location in the fam 17h+ CPUs and accessing the legacy