diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
index 3b05ae9fdc..d052b48e0e 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
@@ -40,17 +40,17 @@ chip soc/intel/skylake
 			register "PcieRpClkReqSupport[0]"		= "true"
 			register "PcieRpClkReqNumber[0]"		= "0"
 			register "PcieRpClkSrcNumber[0]"		= "0"
-			register "PcieRpAdvancedErrorReporting[0]"	= "1"
+			register "PcieRpAdvancedErrorReporting[0]"	= "true"
 			register "PcieRpLtrEnable[0]"			= "true"
 			device generic 0 alias dgpu on end
 		end
 
 		# Ethernet (clobbers RP8)
 		device ref gbe on
-			register "LanClkReqSupported"			= "1"
+			register "LanClkReqSupported"			= "true"
 			register "LanClkReqNumber"			= "1"
-			register "EnableLanLtr"				= "1"
-			register "EnableLanK1Off"			= "1"
+			register "EnableLanLtr"				= "true"
+			register "EnableLanK1Off"			= "true"
 		end
 
 		# M.2 WLAN - x1
@@ -58,8 +58,9 @@ chip soc/intel/skylake
 			register "PcieRpClkReqSupport[6]"		= "true"
 			register "PcieRpClkReqNumber[6]"		= "2"
 			register "PcieRpClkSrcNumber[6]"		= "2"
-			register "PcieRpAdvancedErrorReporting[6]"	= "1"
+			register "PcieRpAdvancedErrorReporting[6]"	= "true"
 			register "PcieRpLtrEnable[6]"			= "true"
+                        smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X"
 		end
 
 		# M.2 WWAN - x2
@@ -67,8 +68,9 @@ chip soc/intel/skylake
 			register "PcieRpClkReqSupport[4]"		= "true"
 			register "PcieRpClkReqNumber[4]"		= "3"
 			register "PcieRpClkSrcNumber[4]"		= "3"
-			register "PcieRpAdvancedErrorReporting[4]"	= "1"
+			register "PcieRpAdvancedErrorReporting[4]"	= "true"
 			register "PcieRpLtrEnable[4]"			= "true"
+                        smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X"
 		end
 
 		# TB3 (Alpine Ridge LP) - x2
@@ -76,9 +78,9 @@ chip soc/intel/skylake
 			register "PcieRpClkReqSupport[8]"		= "true"
 			register "PcieRpClkReqNumber[8]"		= "4"
 			register "PcieRpClkSrcNumber[8]"		= "4"
-			register "PcieRpAdvancedErrorReporting[8]"	= "1"
+			register "PcieRpAdvancedErrorReporting[8]"	= "true"
 			register "PcieRpLtrEnable[8]"			= "true"
-			register "PcieRpHotPlug[8]"			= "1"
+			register "PcieRpHotPlug[8]"			= "true"
 		end
 
 		# M.2 2280 caddy - x2
@@ -86,8 +88,9 @@ chip soc/intel/skylake
 			register "PcieRpClkReqSupport[10]"		= "true"
 			register "PcieRpClkReqNumber[10]"		= "5"
 			register "PcieRpClkSrcNumber[10]"		= "5"
-			register "PcieRpAdvancedErrorReporting[10]"	= "1"
+			register "PcieRpAdvancedErrorReporting[10]"	= "true"
 			register "PcieRpLtrEnable[10]"			= "true"
+                        smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 Sub Card" "SlotDataBusWidth2X"
 		end
 	end
 end
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
index 6a933c42c8..78a1a22eef 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
@@ -40,7 +40,7 @@ chip soc/intel/skylake
 			register "PcieRpClkReqSupport[0]"		= "true"
 			register "PcieRpClkReqNumber[0]"		= "0"
 			register "PcieRpClkSrcNumber[0]"		= "0"
-			register "PcieRpAdvancedErrorReporting[0]"	= "1"
+			register "PcieRpAdvancedErrorReporting[0]"	= "true"
 			register "PcieRpLtrEnable[0]"			= "true"
 			device generic 0 alias dgpu on end
 		end
@@ -50,16 +50,17 @@ chip soc/intel/skylake
 			register "PcieRpClkReqSupport[3]"		= "true"
 			register "PcieRpClkReqNumber[3]"		= "1"
 			register "PcieRpClkSrcNumber[3]"		= "1"
-			register "PcieRpAdvancedErrorReporting[3]"	= "1"
+			register "PcieRpAdvancedErrorReporting[3]"	= "true"
 			register "PcieRpLtrEnable[3]"			= "true"
+                        smbios_slot_desc "SlotTypeM2Socket2" "SlotLengthOther" "M.2/B 3042/2242" "SlotDataBusWidth2X"
 		end
 
 		# Ethernet (clobbers RP8)
 		device ref gbe on
-			register "LanClkReqSupported"			= "1"
+			register "LanClkReqSupported"			= "true"
 			register "LanClkReqNumber"			= "2"
-			register "EnableLanLtr"				= "1"
-			register "EnableLanK1Off"			= "1"
+			register "EnableLanLtr"				= "true"
+			register "EnableLanK1Off"			= "true"
 		end
 
 		# M.2 WLAN - x1
@@ -67,8 +68,9 @@ chip soc/intel/skylake
 			register "PcieRpClkReqSupport[6]"		= "true"
 			register "PcieRpClkReqNumber[6]"		= "3"
 			register "PcieRpClkSrcNumber[6]"		= "3"
-			register "PcieRpAdvancedErrorReporting[6]"	= "1"
+			register "PcieRpAdvancedErrorReporting[6]"	= "true"
 			register "PcieRpLtrEnable[6]"			= "true"
+                        smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X"
 		end
 
 		# TB3 (Alpine Ridge LP) - x2
@@ -76,9 +78,9 @@ chip soc/intel/skylake
 			register "PcieRpClkReqSupport[4]"		= "true"
 			register "PcieRpClkReqNumber[4]"		= "4"
 			register "PcieRpClkSrcNumber[4]"		= "4"
-			register "PcieRpAdvancedErrorReporting[4]"	= "1"
+			register "PcieRpAdvancedErrorReporting[4]"	= "true"
 			register "PcieRpLtrEnable[4]"			= "true"
-			register "PcieRpHotPlug[4]"			= "1"
+			register "PcieRpHotPlug[4]"			= "true"
 		end
 
 		# M.2 2280 SSD - x2
@@ -86,8 +88,9 @@ chip soc/intel/skylake
 			register "PcieRpClkReqSupport[8]"		= "true"
 			register "PcieRpClkReqNumber[8]"		= "5"
 			register "PcieRpClkSrcNumber[8]"		= "5"
-			register "PcieRpAdvancedErrorReporting[8]"	= "1"
+			register "PcieRpAdvancedErrorReporting[8]"	= "true"
 			register "PcieRpLtrEnable[8]"			= "true"
+                        smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth2X"
 		end
 	end
 end