erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

soc/intel,mb/google: Use the correct SoC config

Browse source 
Change-Id: I657a4d45901f6b2bab8daa6c93509190896cab62
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86748
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kapil Porwal 2025-03-06 13:57:54 +05:30 • committed by Subrata Banik
commit 17da392ae8
2 changed files with 1 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

6
src/soc/intel/pantherlake/Kconfig
View file

@ -127,12 +127,6 @@ config SOC_INTEL_PANTHERLAKE_H
help
Choose this option if the mainboard is built using PTL-H 4Xe system-on-a-chip (SoC).
config SOC_INTEL_WILDCATLAKE
bool
select SOC_INTEL_PANTHERLAKE_U_H
help
Choose this option if the mainboard is built using WCL system-on-a-chip (SoC).
if SOC_INTEL_PANTHERLAKE_BASE
config SOC_INTEL_PANTHERLAKE_TCSS_USB4_SUPPORT