diff --git a/Makefile b/Makefile
index 78fbf74be0..a9e381b402 100644
--- a/Makefile
+++ b/Makefile
@@ -113,6 +113,7 @@ else
 
 include $(HAVE_DOTCONFIG)
 
+ARCHDIR-$(CONFIG_ARCH_AARCH64)   := aarch64
 ARCHDIR-$(CONFIG_ARCH_ARM)   := arm
 ARCHDIR-$(CONFIG_ARCH_X86)     := x86
 
diff --git a/src/Kconfig b/src/Kconfig
index 05ac44c642..cd9553e6a1 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -226,6 +226,10 @@ config ARCH_ARM
 	bool
 	default n
 
+config ARCH_AARCH64
+	bool
+	default n
+
 # Warning: The file is included whether or not the if is here.
 # but the if controls how the evaluation occurs.
 if ARCH_X86
@@ -236,6 +240,10 @@ if ARCH_ARM
 source src/arch/arm/Kconfig
 endif
 
+if ARCH_AARCH64
+source src/arch/aarch64/Kconfig
+endif
+
 config HAVE_ARCH_MEMSET
 	bool
 	default n
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index 6674163cfa..23d46b48b1 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -1,12 +1,9 @@
 # Warning: This file is included whether or not the if is here.
 # The if controls how the evaluation occurs.
 # (See also src/Kconfig)
-if ARCH_ARM
 
 source src/cpu/armltd/Kconfig
 
-endif	# ARCH_ARM
-
 if ARCH_X86
 
 source src/cpu/amd/Kconfig
diff --git a/src/cpu/armltd/Kconfig b/src/cpu/armltd/Kconfig
index af0c5c531c..fe41e475ae 100644
--- a/src/cpu/armltd/Kconfig
+++ b/src/cpu/armltd/Kconfig
@@ -1 +1,2 @@
 source src/cpu/armltd/cortex-a9/Kconfig
+source src/cpu/armltd/armv8/Kconfig
diff --git a/src/cpu/armltd/Makefile.inc b/src/cpu/armltd/Makefile.inc
index 014742f056..87bd7386bb 100644
--- a/src/cpu/armltd/Makefile.inc
+++ b/src/cpu/armltd/Makefile.inc
@@ -1 +1,2 @@
 subdirs-$(CONFIG_CPU_ARMLTD_CORTEX_A9) += cortex-a9
+subdirs-$(CONFIG_CPU_ARMLTD_CORTEX_A9) += armv8
diff --git a/src/cpu/armltd/armv8/Kconfig b/src/cpu/armltd/armv8/Kconfig
new file mode 100644
index 0000000000..6cd422a464
--- /dev/null
+++ b/src/cpu/armltd/armv8/Kconfig
@@ -0,0 +1,15 @@
+config CPU_ARMLTD_ARMV8
+	depends on ARCH_AARCH64
+	bool
+	select EARLY_CONSOLE
+	default n
+
+if CPU_ARMLTD_ARMV8
+
+config BOOTBLOCK_CPU_INIT
+	string
+	default "cpu/armltd/armv8/bootblock.c"
+	help
+	  CPU/SoC-specific bootblock code.
+endif
+
diff --git a/src/cpu/armltd/armv8/Makefile.inc b/src/cpu/armltd/armv8/Makefile.inc
new file mode 100644
index 0000000000..f1a3689691
--- /dev/null
+++ b/src/cpu/armltd/armv8/Makefile.inc
@@ -0,0 +1,3 @@
+ramstage-y += cache.c
+romstage-y += cache.c
+bootblock-y += cache.c
diff --git a/src/cpu/armltd/armv8/bootblock.c b/src/cpu/armltd/armv8/bootblock.c
new file mode 100644
index 0000000000..8925439d2a
--- /dev/null
+++ b/src/cpu/armltd/armv8/bootblock.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+void bootblock_cpu_init(void);
+void bootblock_cpu_init(void)
+{
+}
diff --git a/src/cpu/armltd/armv8/cache.c b/src/cpu/armltd/armv8/cache.c
new file mode 100644
index 0000000000..dd00faf8ef
--- /dev/null
+++ b/src/cpu/armltd/armv8/cache.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <aarch64.h>
+
+/*
+ * Sets L2 cache related parameters before enabling data cache
+ */
+void v8_outer_cache_enable(void)
+{
+}
+
+/* stubs so we don't need weak symbols in cache_v8.c */
+void v8_outer_cache_disable(void)
+{
+}
+
+void v8_outer_cache_flush_all(void)
+{
+}
+
+void v8_outer_cache_inval_all(void)
+{
+}
+
+void v8_outer_cache_flush_range(u32 start, u32 end)
+{
+}
+
+void v8_outer_cache_inval_range(u32 start, u32 end)
+{
+}