From 16bafecfaa89cdd1005372fd3432d69bd5b3a24d Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sat, 3 Dec 2016 09:54:28 +0100 Subject: [PATCH] UPSTREAM: mb/lenovo/x60: Remove PCI reset code from romstage Commit bf264e94 (i945:) adds a PCI reset to the romstage, and commit bc8613ec (Fix i945 based boards) fixes that to use the correct delay of 200 ms. This code was then copied over, when adding support for the Lenovo X60. The reset was related to the shipped crypto card on the Roda RK886EX and Kontron 986LCD-M, so is not needed on the Lenovo X60. So remove it. TEST=Build and boot on Lenovo X60t. BUG=None BRANCH=None Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/17703 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Nico Huber Change-Id: Ia37d9f0ecf5655531616edb20b53757d5d47b42f Reviewed-on: https://chromium-review.googlesource.com/422951 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Aaron Durbin --- src/mainboard/lenovo/x60/romstage.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index c735ce2f01..53a0151fb9 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -219,11 +219,6 @@ void mainboard_romstage_entry(unsigned long bist) if (bist == 0) enable_lapic(); - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); - /* Enable GPIOs */ pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* 0x4c == GC */