diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
index 827eec302d..5c26bcd685 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
@@ -57,8 +57,7 @@ typedef struct {
/** Offset 0x0060 - Serial Io Uart Debug Mode
Select SerialIo Uart Controller mode
- 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
- 4:SerialIoUartSkipInit
+ 1:SerialIoUartPci, 4:SerialIoUartSkipInit
**/
UINT8 SerialIoUartDebugMode;
@@ -941,8 +940,8 @@ typedef struct {
**/
UINT8 DIMMRONT;
-/** Offset 0x0260 - Write Drive Strength/Equalization 2D
- Enables/Disable Write Drive Strength/Equalization 2D
+/** Offset 0x0260 - Write Drive Strength Training
+ Enables/Disable Write Drive Strength Training
$EN_DIS
**/
UINT8 WRDSEQT;
@@ -1241,9 +1240,11 @@ typedef struct {
**/
UINT8 ChHashInterleaveBit;
-/** Offset 0x02BB - Reserved
+/** Offset 0x02BB - Write Equalization Training
+ Enables/Disables Write Equalization Training
+ $EN_DIS
**/
- UINT8 Reserved25;
+ UINT8 WREQT;
/** Offset 0x02BC - Ch Hash Mask
Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
@@ -1253,7 +1254,7 @@ typedef struct {
/** Offset 0x02BE - Reserved
**/
- UINT8 Reserved26;
+ UINT8 Reserved25;
/** Offset 0x02BF - Throttler CKEMin Timer
Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
@@ -1332,7 +1333,7 @@ typedef struct {
/** Offset 0x02CB - Reserved
**/
- UINT8 Reserved27[5];
+ UINT8 Reserved26[5];
/** Offset 0x02D0 - DDR Phy Safe Mode Support
DdrSafeMode[0]: Basic PM Features, DdrSafeMode[1]: Spine Gating, DdrSafeMode[2]:
@@ -1354,7 +1355,7 @@ typedef struct {
/** Offset 0x02D6 - Reserved
**/
- UINT8 Reserved28[8];
+ UINT8 Reserved27[8];
/** Offset 0x02DE - RMTLoopCount
Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
@@ -1390,7 +1391,7 @@ typedef struct {
/** Offset 0x02E7 - Reserved
**/
- UINT8 Reserved29;
+ UINT8 Reserved28;
/** Offset 0x02E8 - Margin limit check L2
Margin limit check L2 threshold: 100=Default
@@ -1405,7 +1406,7 @@ typedef struct {
/** Offset 0x02EB - Reserved
**/
- UINT8 Reserved30;
+ UINT8 Reserved29;
/** Offset 0x02EC - LP5 Command Pins Mapping
BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
@@ -1427,7 +1428,7 @@ typedef struct {
/** Offset 0x02EF - Reserved
**/
- UINT8 Reserved31[43];
+ UINT8 Reserved30[43];
/** Offset 0x031A - Read Vref Decap Training*
Enable/Disable Read Timing Centering Training with SR stress*
@@ -1455,7 +1456,7 @@ typedef struct {
/** Offset 0x031E - Reserved
**/
- UINT8 Reserved32[17];
+ UINT8 Reserved31[17];
/** Offset 0x032F - Board Type
MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
@@ -1479,7 +1480,7 @@ typedef struct {
/** Offset 0x0341 - Reserved
**/
- UINT8 Reserved33;
+ UINT8 Reserved32;
/** Offset 0x0342 - Skip external display device scanning
Enable: Do not scan for external display device, Disable (Default): Scan external
@@ -1607,7 +1608,7 @@ typedef struct {
/** Offset 0x04D6 - Reserved
**/
- UINT8 Reserved34[2];
+ UINT8 Reserved33[2];
/** Offset 0x04D8 - DMIC ClkA Pin Muxing (N - DMIC number)
Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKA_*
@@ -1622,7 +1623,7 @@ typedef struct {
/** Offset 0x04E1 - Reserved
**/
- UINT8 Reserved35[3];
+ UINT8 Reserved34[3];
/** Offset 0x04E4 - DMIC Data Pin Muxing
Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_*
@@ -1636,7 +1637,7 @@ typedef struct {
/** Offset 0x04F3 - Reserved
**/
- UINT8 Reserved36[117];
+ UINT8 Reserved35[117];
/** Offset 0x0568 - Enable HD Audio SoundWire#N Link
Enable/disable HD Audio SNDW#N link. Muxed with HDA.
@@ -1657,7 +1658,7 @@ typedef struct {
/** Offset 0x056F - Reserved
**/
- UINT8 Reserved37[45];
+ UINT8 Reserved36[45];
/** Offset 0x059C - iDisplay Audio Codec disconnection
0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
@@ -1667,7 +1668,7 @@ typedef struct {
/** Offset 0x059D - Reserved
**/
- UINT8 Reserved38[5];
+ UINT8 Reserved37[5];
/** Offset 0x05A2 - HDA Power/Clock Gating (PGD/CGD)
Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1:
@@ -1678,7 +1679,7 @@ typedef struct {
/** Offset 0x05A3 - Reserved
**/
- UINT8 Reserved39;
+ UINT8 Reserved38;
/** Offset 0x05A4 - Audio Sub System IDs
Set default Audio Sub System IDs. If its set to 0 then value from Strap is used.
@@ -1687,7 +1688,7 @@ typedef struct {
/** Offset 0x05A8 - Reserved
**/
- UINT8 Reserved40;
+ UINT8 Reserved39;
/** Offset 0x05A9 - PCH LPC Enhance the port 8xh decoding
Original LPC only decodes one byte of port 80h.
@@ -1707,7 +1708,7 @@ typedef struct {
/** Offset 0x05CE - Reserved
**/
- UINT8 Reserved41[46];
+ UINT8 Reserved40[46];
/** Offset 0x05FC - Enable PCIE RP Mask
Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
@@ -1723,7 +1724,7 @@ typedef struct {
/** Offset 0x0601 - Reserved
**/
- UINT8 Reserved42[3];
+ UINT8 Reserved41[3];
/** Offset 0x0604 - Serial Io Uart Debug Mmio Base
Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdLpssUartMode
@@ -1800,7 +1801,7 @@ typedef struct {
/** Offset 0x061A - Reserved
**/
- UINT8 Reserved43[2];
+ UINT8 Reserved42[2];
/** Offset 0x061C - HECI Timeouts
0: Disable, 1: Enable (Default) timeout check for HECI
@@ -1853,7 +1854,7 @@ typedef struct {
/** Offset 0x0624 - Reserved
**/
- UINT8 Reserved44[2];
+ UINT8 Reserved43[2];
/** Offset 0x0626 - ISA Serial Base selection
Select ISA Serial Base address. Default is 0x3F8.
@@ -1874,7 +1875,7 @@ typedef struct {
/** Offset 0x062A - Reserved
**/
- UINT8 Reserved45[26];
+ UINT8 Reserved44[26];
/** Offset 0x0644 - Enable SMBus
Enable/disable SMBus controller.
@@ -1895,7 +1896,7 @@ typedef struct {
/** Offset 0x0647 - Reserved
**/
- UINT8 Reserved46;
+ UINT8 Reserved45;
/** Offset 0x0648 - SMBUS Base Address
SMBUS Base Address (IO space).
@@ -1910,7 +1911,7 @@ typedef struct {
/** Offset 0x064B - Reserved
**/
- UINT8 Reserved47[13];
+ UINT8 Reserved46[13];
/** Offset 0x0658 - Smbus dynamic power gating
Disable or Enable Smbus dynamic power gating.
@@ -1933,7 +1934,7 @@ typedef struct {
/** Offset 0x065B - Reserved
**/
- UINT8 Reserved48[18];
+ UINT8 Reserved47[18];
/** Offset 0x066D - Over clocking support
Over clocking support; 0: Disable; 1: Enable
@@ -1943,7 +1944,7 @@ typedef struct {
/** Offset 0x066E - Reserved
**/
- UINT8 Reserved49;
+ UINT8 Reserved48;
/** Offset 0x066F - Realtime Memory Timing
0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
@@ -2006,7 +2007,7 @@ typedef struct {
/** Offset 0x067B - Reserved
**/
- UINT8 Reserved50[2];
+ UINT8 Reserved49[2];
/** Offset 0x067D - TjMax Offset
TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
@@ -2016,7 +2017,7 @@ typedef struct {
/** Offset 0x067E - Reserved
**/
- UINT8 Reserved51[48];
+ UINT8 Reserved50[48];
/** Offset 0x06AE - Core VF Point Offset
Array used to specifies the Core Voltage Offset applied to the each selected VF
@@ -2038,7 +2039,7 @@ typedef struct {
/** Offset 0x06EA - Reserved
**/
- UINT8 Reserved52[26];
+ UINT8 Reserved51[26];
/** Offset 0x0704 - Per Core Max Ratio override
Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
@@ -2049,7 +2050,7 @@ typedef struct {
/** Offset 0x0705 - Reserved
**/
- UINT8 Reserved53[25];
+ UINT8 Reserved52[25];
/** Offset 0x071E - Per Core Current Max Ratio
Array for the Per Core Max Ratio
@@ -2058,7 +2059,7 @@ typedef struct {
/** Offset 0x0726 - Reserved
**/
- UINT8 Reserved54[8];
+ UINT8 Reserved53[8];
/** Offset 0x072E - Pvd Ratio Threshold for SOC/CPU die
Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio
@@ -2071,7 +2072,7 @@ typedef struct {
/** Offset 0x072F - Reserved
**/
- UINT8 Reserved55[65];
+ UINT8 Reserved54[65];
/** Offset 0x0770 - CPU BCLK OC Frequency
CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz 0 - Auto. Range is
@@ -2081,7 +2082,7 @@ typedef struct {
/** Offset 0x0774 - Reserved
**/
- UINT8 Reserved56[13];
+ UINT8 Reserved55[13];
/** Offset 0x0781 - Avx2 Voltage Guardband Scaling Factor
AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in
@@ -2096,7 +2097,7 @@ typedef struct {
/** Offset 0x0783 - Reserved
**/
- UINT8 Reserved57[5];
+ UINT8 Reserved56[5];
/** Offset 0x0788 - Enable PCH ISH Controller
0: Disable, 1: Enable (Default) ISH Controller
@@ -2106,7 +2107,7 @@ typedef struct {
/** Offset 0x0789 - Reserved
**/
- UINT8 Reserved58;
+ UINT8 Reserved57;
/** Offset 0x078A - BiosSize
The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard !=
@@ -2141,7 +2142,7 @@ typedef struct {
/** Offset 0x0790 - Reserved
**/
- UINT8 Reserved59[3];
+ UINT8 Reserved58[3];
/** Offset 0x0793 - MKTME Key-Id Bits Override Enable
Configure Trust Domain Extension (TDX) to isolate VMs from Virtual-Machine Manager
@@ -2152,7 +2153,7 @@ typedef struct {
/** Offset 0x0794 - Reserved
**/
- UINT8 Reserved60[4];
+ UINT8 Reserved59[4];
/** Offset 0x0798 - TME Exclude Base Address
TME Exclude Base Address.
@@ -2166,7 +2167,7 @@ typedef struct {
/** Offset 0x07A8 - Reserved
**/
- UINT8 Reserved61[14];
+ UINT8 Reserved60[14];
/** Offset 0x07B6 - BIST on Reset
Enable/Disable BIST (Built-In Self Test) on reset. 0: Disable; 1: Enable.
@@ -2176,7 +2177,7 @@ typedef struct {
/** Offset 0x07B7 - Reserved
**/
- UINT8 Reserved62;
+ UINT8 Reserved61;
/** Offset 0x07B8 - Enable or Disable VMX
Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities
@@ -2246,7 +2247,7 @@ typedef struct {
/** Offset 0x07C2 - Reserved
**/
- UINT8 Reserved63[6];
+ UINT8 Reserved62[6];
/** Offset 0x07C8 - PrmrrSize
Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
@@ -2274,7 +2275,7 @@ typedef struct {
/** Offset 0x07D2 - Reserved
**/
- UINT8 Reserved64[98];
+ UINT8 Reserved63[98];
/** Offset 0x0834 - SinitMemorySize
Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
@@ -2341,7 +2342,7 @@ typedef struct {
/** Offset 0x086E - Reserved
**/
- UINT8 Reserved65[2];
+ UINT8 Reserved64[2];
/** Offset 0x0870 - Platform Power Pmax
PSYS PMax power, defined in 1/8 Watt increments. 0 - Auto Specified in 1/8
@@ -2393,7 +2394,7 @@ typedef struct {
/** Offset 0x08BA - Reserved
**/
- UINT8 Reserved66[26];
+ UINT8 Reserved65[26];
/** Offset 0x08D4 - Icc Max limit
Voltage Regulator Current Limit (Icc Max). This value represents the Maximum instantaneous
@@ -2405,7 +2406,7 @@ typedef struct {
/** Offset 0x08E0 - Reserved
**/
- UINT8 Reserved67[42];
+ UINT8 Reserved66[42];
/** Offset 0x090A - Thermal Design Current enable/disable
Thermal Design Current enable/disable; 0: Disable; 1: Enable. [0] for IA,
@@ -2415,7 +2416,7 @@ typedef struct {
/** Offset 0x0910 - Reserved
**/
- UINT8 Reserved68[6];
+ UINT8 Reserved67[6];
/** Offset 0x0916 - Disable Fast Slew Rate for Deep Package C States for VR domains
This option needs to be configured to reduce acoustic noise during deeper C states.
@@ -2437,7 +2438,7 @@ typedef struct {
/** Offset 0x0922 - Reserved
**/
- UINT8 Reserved69[6];
+ UINT8 Reserved68[6];
/** Offset 0x0928 - Thermal Design Current time window
Auto = 0 is default. Range is from 1ms to 448s. 0: Auto. [0] for IA, [1]
@@ -2453,7 +2454,7 @@ typedef struct {
/** Offset 0x0946 - Reserved
**/
- UINT8 Reserved70[2];
+ UINT8 Reserved69[2];
/** Offset 0x0948 - DLVR RFI Enable
Enable/Disable DLVR RFI frequency hopping. 0: Disable; 1: Enable.
@@ -2462,18 +2463,18 @@ typedef struct {
UINT8 DlvrRfiEnable;
/** Offset 0x0949 - Pcore VR Hysteresis time window
- 0 is default. Range of PcoreHysteresisWindow from 1ms to 50ms.
+ Enable/Disable DLVR RFI frequency hopping. 0: Disable; 1: Enable.
**/
UINT8 PcoreHysteresisWindow;
/** Offset 0x094A - Ecore VR Hysteresis time window
- 0 is default. Range of EcoreHysteresisWindow from 1ms to 50ms.
+ Enable/Disable DLVR RFI frequency hopping. 0: Disable; 1: Enable.
**/
UINT8 EcoreHysteresisWindow;
/** Offset 0x094B - Reserved
**/
- UINT8 Reserved71[11];
+ UINT8 Reserved70[11];
/** Offset 0x0956 - VR Fast Vmode ICC Limit support
Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds
@@ -2498,7 +2499,7 @@ typedef struct {
/** Offset 0x096E - Reserved
**/
- UINT8 Reserved72[28];
+ UINT8 Reserved71[28];
/** Offset 0x098A - PCH Port80 Route
Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
@@ -2515,7 +2516,7 @@ typedef struct {
/** Offset 0x098C - Reserved
**/
- UINT8 Reserved73[4];
+ UINT8 Reserved72[4];
/** Offset 0x0990 - PMR Size
Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
@@ -2541,7 +2542,7 @@ typedef struct {
/** Offset 0x0997 - Reserved
**/
- UINT8 Reserved74;
+ UINT8 Reserved73;
/** Offset 0x0998 - Base addresses for VT-d function MMIO access
Base addresses for VT-d MMIO access per VT-d engine
@@ -2550,7 +2551,7 @@ typedef struct {
/** Offset 0x09BC - Reserved
**/
- UINT8 Reserved75[20];
+ UINT8 Reserved74[20];
/** Offset 0x09D0 - MMIO Size
Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
@@ -2565,7 +2566,7 @@ typedef struct {
/** Offset 0x09D4 - Reserved
**/
- UINT8 Reserved76[36];
+ UINT8 Reserved75[36];
/** Offset 0x09F8 - Enable above 4GB MMIO resource support
Enable/disable above 4GB MMIO resource support
@@ -2581,7 +2582,7 @@ typedef struct {
/** Offset 0x09FA - Reserved
**/
- UINT8 Reserved77[10];
+ UINT8 Reserved76[10];
/** Offset 0x0A04 - Enable/Disable CrashLog Device
Enable or Disable CrashLog/Telemetry Device 0- Disable, 1- Enable
@@ -2591,7 +2592,7 @@ typedef struct {
/** Offset 0x0A08 - Reserved
**/
- UINT8 Reserved78[20];
+ UINT8 Reserved77[20];
/** Offset 0x0A1C - Platform Debug Option
Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n
@@ -2608,7 +2609,7 @@ typedef struct {
/** Offset 0x0A1D - Reserved
**/
- UINT8 Reserved79[14];
+ UINT8 Reserved78[14];
/** Offset 0x0A2B - Program GPIOs for LFP on DDI port-A device
0=Disabled,1(Default)=eDP, 2=MIPI DSI
@@ -2618,7 +2619,7 @@ typedef struct {
/** Offset 0x0A2C - Reserved
**/
- UINT8 Reserved80[2];
+ UINT8 Reserved79[2];
/** Offset 0x0A2E - Program GPIOs for LFP on DDI port-B device
0(Default)=Disabled,1=eDP, 2=MIPI DSI
@@ -2712,7 +2713,7 @@ typedef struct {
/** Offset 0x0A3D - Reserved
**/
- UINT8 Reserved81[3];
+ UINT8 Reserved80[3];
/** Offset 0x0A40 - Temporary MMIO address for GMADR
The reference code will use this as Temporary MMIO address space to access GMADR
@@ -2731,7 +2732,7 @@ typedef struct {
/** Offset 0x0A50 - Reserved
**/
- UINT8 Reserved82[2];
+ UINT8 Reserved81[2];
/** Offset 0x0A52 - Enable/Disable Memory Bandwidth Compression
0=Disable, 1(Default)=Enable
@@ -2761,7 +2762,7 @@ typedef struct {
/** Offset 0x0A56 - Reserved
**/
- UINT8 Reserved83[2];
+ UINT8 Reserved82[2];
/** Offset 0x0A58 - Intel Graphics VBT (Video BIOS Table) Size
Size of Internal Graphics VBT Image
@@ -2770,7 +2771,7 @@ typedef struct {
/** Offset 0x0A5C - Reserved
**/
- UINT8 Reserved84[4];
+ UINT8 Reserved83[4];
/** Offset 0x0A60 - Graphics Configuration Ptr
Points to VBT
@@ -2831,7 +2832,7 @@ typedef struct {
/** Offset 0x0A83 - Reserved
**/
- UINT8 Reserved85[4];
+ UINT8 Reserved84[4];
/** Offset 0x0A87 - TCSS Type C Port 0
Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
@@ -2863,7 +2864,7 @@ typedef struct {
/** Offset 0x0A8B - Reserved
**/
- UINT8 Reserved86;
+ UINT8 Reserved85;
/** Offset 0x0A8C - TypeC port GPIO setting
GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined
@@ -2931,7 +2932,7 @@ typedef struct {
/** Offset 0x0AC9 - Reserved
**/
- UINT8 Reserved87;
+ UINT8 Reserved86;
/** Offset 0x0ACA - DLL Weak Lock Support
Enables/Disable DLL Weak Lock Support
@@ -2941,7 +2942,7 @@ typedef struct {
/** Offset 0x0ACB - Reserved
**/
- UINT8 Reserved88;
+ UINT8 Reserved87;
/** Offset 0x0ACC - Rx DQS Delay Comp Support
Enables/Disable Rx DQS Delay Comp Support
@@ -2951,7 +2952,7 @@ typedef struct {
/** Offset 0x0ACD - Reserved
**/
- UINT8 Reserved89[2];
+ UINT8 Reserved88[2];
/** Offset 0x0ACF - Mrc Failure On Unsupported Dimm
Enables/Disable Mrc Failure On Unsupported Dimm
@@ -2961,7 +2962,7 @@ typedef struct {
/** Offset 0x0AD0 - Reserved
**/
- UINT8 Reserved90[4];
+ UINT8 Reserved89[4];
/** Offset 0x0AD4 - DynamicMemoryBoost
Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is
@@ -2979,7 +2980,7 @@ typedef struct {
/** Offset 0x0ADC - Reserved
**/
- UINT8 Reserved91[9];
+ UINT8 Reserved90[9];
/** Offset 0x0AE5 - Vref Offset
Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset
@@ -2990,7 +2991,7 @@ typedef struct {
/** Offset 0x0AE6 - Reserved
**/
- UINT8 Reserved92[2];
+ UINT8 Reserved91[2];
/** Offset 0x0AE8 - tRRSG Delta
Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
@@ -3106,7 +3107,7 @@ typedef struct {
/** Offset 0x0AF8 - Reserved
**/
- UINT8 Reserved93[41];
+ UINT8 Reserved92[41];
/** Offset 0x0B21 - Channel to CKD QCK Mapping
Specify Channel to CKD QCK Mapping for CH0D0/CH0D1/CH1D0&CH1D1
@@ -3120,7 +3121,7 @@ typedef struct {
/** Offset 0x0B31 - Reserved
**/
- UINT8 Reserved94[55];
+ UINT8 Reserved93[55];
} FSP_M_CONFIG;
/** Fsp M UPD Configuration
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
index 0b540c7e14..b5194418b1 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
@@ -2337,9 +2337,17 @@ typedef struct {
**/
UINT8 PchHdaLinkFrequency;
-/** Offset 0x149B - Reserved
+/** Offset 0x149B - HD Audio Microphone Privacy Mode
+ HD Audio Microphone Privacy Mode: 0: No Microphone Privacy Support; 1: HW Managed
+ Microphone Privacy; 2: FW Managed Microphone Privacy; 3: Force Microphone Mute
+ 0: No Microphone Privacy Support, 1: HW Managed Microphone Privacy, 2: FW Managed
+ Microphone Privacy, 3: Force Microphone Mute
**/
- UINT8 Reserved59[2];
+ UINT8 PchHdaMicPrivacyMode;
+
+/** Offset 0x149C - Reserved
+**/
+ UINT8 Reserved59;
/** Offset 0x149D - HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode
HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode: 0: Disable, 1: Enable
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
index 4171f4a1da..c89cf2cab1 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
@@ -15,7 +15,6 @@
@par Specification Reference:
**/
-
#ifndef _MEM_INFO_HOB_H_
#define _MEM_INFO_HOB_H_
@@ -36,6 +35,9 @@ extern EFI_GUID gSiMemoryPlatformDataGuid;
#define _MAX_RANK_IN_CHANNEL (4) ///< The maximum number of ranks per channel.
#define _MAX_SDRAM_IN_DIMM (5) ///< The maximum number of SDRAMs per DIMM.
+// Must match the corresponding definition in CMrcExtTypes.h
+#define PPR_REQUEST_MAX (2)
+
// Must match definitions in
// Intel\OneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h
#define HOB_MAX_SAGV_POINTS 4
@@ -360,6 +362,7 @@ typedef struct {
BOOLEAN MixedEccDimms; ///< TRUE if both ECC and nonECC Dimms were detected in the system
UINT8 MaxRankCapacity; ///< Maximum possible rank capacity in [GB]
UINT16 PprFailingChannelBitMask; ///< PPR failing channel mask
+ BOOLEAN PprTargetedStatus[PPR_REQUEST_MAX]; ///< PPR status of each Targeted PPR request (0 = Targeted PPR was successful, 1 = PPR failed)
} MEMORY_INFO_DATA_HOB;
/**