diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c index 80f186ed03..e70ba50498 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c @@ -1,14 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include "pin_mux.h" void mainboard_silicon_init_params(FSP_S_CONFIG *supd) { - /* - * FSP defaults to pins that are used for LPC; given that - * coreboot only supports eSPI, set these pins accordingly. - */ - supd->CnviRfResetPinMux = 0x194ce404; // GPP_F4 - supd->CnviClkreqPinMux = 0x294ce605; // GPP_F5 - supd->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13 + configure_pin_mux(supd); } diff --git a/src/mainboard/starlabs/common/Makefile.mk b/src/mainboard/starlabs/common/Makefile.mk index 3979986e57..3329eb0554 100644 --- a/src/mainboard/starlabs/common/Makefile.mk +++ b/src/mainboard/starlabs/common/Makefile.mk @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only subdirs-$(CONFIG_VENDOR_STARLABS) += smbios +subdirs-$(CONFIG_VENDOR_STARLABS) += pin_mux diff --git a/src/mainboard/starlabs/common/pin_mux/Makefile.mk b/src/mainboard/starlabs/common/pin_mux/Makefile.mk new file mode 100644 index 0000000000..2249df0b3c --- /dev/null +++ b/src/mainboard/starlabs/common/pin_mux/Makefile.mk @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += tigerlake.c +ramstage-$(CONFIG_SOC_INTEL_ALDERLAKE) += alderlake.c +ramstage-$(CONFIG_SOC_INTEL_METEORLAKE) += meteorlake.c + +CPPFLAGS_common += -I$(src)/mainboard/starlabs/common/pin_mux diff --git a/src/mainboard/starlabs/common/pin_mux/alderlake.c b/src/mainboard/starlabs/common/pin_mux/alderlake.c new file mode 100644 index 0000000000..1869b631e0 --- /dev/null +++ b/src/mainboard/starlabs/common/pin_mux/alderlake.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "pin_mux.h" + +void configure_pin_mux(FSP_S_CONFIG *supd) +{ + supd->SataPortDevSlpPinMux[0] = 0x59673e0c; + supd->SataPortDevSlpPinMux[1] = 0x5967400d; + supd->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; + supd->PchSerialIoI2cSdaPinMux[1] = 0x1947c606; + supd->PchSerialIoI2cSdaPinMux[4] = 0; + supd->PchSerialIoI2cSdaPinMux[7] = 0x1947d20c; + supd->PchSerialIoI2cSclPinMux[0] = 0x1947a405; + supd->PchSerialIoI2cSclPinMux[1] = 0x1947a607; + supd->PchSerialIoI2cSclPinMux[4] = 0; + supd->PchSerialIoI2cSclPinMux[7] = 0x1947b20d; + supd->IshGpGpioPinMuxing[4] = 0x290ea809; + supd->IshGpGpioPinMuxing[5] = 0x4900aa04; + supd->IshGpGpioPinMuxing[6] = 0x4907ac0c; + supd->IshGpGpioPinMuxing[7] = 0x5900ae0f; + supd->CnviRfResetPinMux = 0x194ce404; + supd->CnviClkreqPinMux = 0x294ce605; +} diff --git a/src/mainboard/starlabs/common/pin_mux/meteorlake.c b/src/mainboard/starlabs/common/pin_mux/meteorlake.c new file mode 100644 index 0000000000..37d1f4aa1a --- /dev/null +++ b/src/mainboard/starlabs/common/pin_mux/meteorlake.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "pin_mux.h" + +void configure_pin_mux(FSP_S_CONFIG *supd) +{ + supd->IshUartRxPinMuxing[1] = 0x146806; + supd->IshUartTxPinMuxing[1] = 0x146807; + supd->IshI2cSdaPinMuxing[2] = 0x143012; + supd->IshI2cSclPinMuxing[2] = 0x143013; + supd->IshSpiMosiPinMuxing[0] = 0x147088; + supd->IshSpiMisoPinMuxing[0] = 0x147087; + supd->IshSpiClkPinMuxing[0] = 0x147086; + supd->IshSpiCsPinMuxing[0] = 0x147085; + supd->SerialIoUartRxPinMuxPolicy[1] = 0x144806; + supd->SerialIoUartTxPinMuxPolicy[1] = 0x144807; + supd->PchSerialIoI2cSdaPinMux[2] = 0x142804; + supd->PchSerialIoI2cSdaPinMux[3] = 0x142806; + supd->PchSerialIoI2cSdaPinMux[4] = 0x15048c; + supd->PchSerialIoI2cSdaPinMux[5] = 0x15088d; + supd->PchSerialIoI2cSclPinMux[2] = 0x142805; + supd->PchSerialIoI2cSclPinMux[3] = 0x142807; + supd->PchSerialIoI2cSclPinMux[4] = 0x15048d; + supd->PchSerialIoI2cSclPinMux[5] = 0x15088c; + supd->SerialIoI3cSdaPinMux[1] = 0x144815; + supd->SerialIoI3cSclPinMux[1] = 0x144816; + supd->SerialIoI3cSclFbPinMux[1] = 0x144818; + supd->IshGpGpioPinMuxing[5] = 0x149016; + supd->IshGpGpioPinMuxing[6] = 0x149017; + supd->IshGpGpioPinMuxing[8] = 0x149014; + supd->IshGpGpioPinMuxing[9] = 0x150897; + supd->IshGpGpioPinMuxing[10] = 0x150490; + supd->IshGpGpioPinMuxing[11] = 0x150889; + supd->SerialIoSpiCsPinMux[0] = 0x14a48a; + supd->SerialIoSpiClkPinMux[0] = 0x14a48b; + supd->SerialIoSpiMisoPinMux[0] = 0x14a48c; + supd->SerialIoSpiMosiPinMux[0] = 0x14a48d; +} diff --git a/src/mainboard/starlabs/common/pin_mux/pin_mux.h b/src/mainboard/starlabs/common/pin_mux/pin_mux.h new file mode 100644 index 0000000000..38c77f4032 --- /dev/null +++ b/src/mainboard/starlabs/common/pin_mux/pin_mux.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef PIN_MUX +#define PIN_MUX + +void configure_pin_mux(FSP_S_CONFIG *supd); + +#endif diff --git a/src/mainboard/starlabs/common/pin_mux/tigerlake.c b/src/mainboard/starlabs/common/pin_mux/tigerlake.c new file mode 100644 index 0000000000..34c1a05b90 --- /dev/null +++ b/src/mainboard/starlabs/common/pin_mux/tigerlake.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "pin_mux.h" + +void configure_pin_mux(FSP_S_CONFIG *supd) +{ + supd->SerialIoUartRxPinMuxPolicy[0] = 0x190B0208; + supd->SerialIoUartTxPinMuxPolicy[0] = 0x190B1209; + supd->SerialIoUartRtsPinMuxPolicy[0] = 0x190B220a; + supd->SerialIoUartCtsPinMuxPolicy[0] = 0x190B320b; + supd->SerialIoUartRxPinMuxPolicy[0] = 0x18050208; + supd->SerialIoUartTxPinMuxPolicy[0] = 0x18051209; + supd->SerialIoUartRtsPinMuxPolicy[0] = 0x1805220c; + supd->SerialIoUartCtsPinMuxPolicy[0] = 0x1805320b; +} diff --git a/src/mainboard/starlabs/starbook/variants/adl/ramstage.c b/src/mainboard/starlabs/starbook/variants/adl/ramstage.c index 9e678def77..e6828e23ca 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/ramstage.c +++ b/src/mainboard/starlabs/starbook/variants/adl/ramstage.c @@ -2,16 +2,11 @@ #include #include +#include "pin_mux.h" void mainboard_silicon_init_params(FSP_S_CONFIG *supd) { - /* - * FSP defaults to pins that are used for LPC; given that - * coreboot only supports eSPI, set these pins accordingly. - */ - supd->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 - supd->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 - supd->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13 + configure_pin_mux(supd); /* * Enable Hot Plug on RP5 to slow down coreboot so that diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/ramstage.c b/src/mainboard/starlabs/starbook/variants/adl_n/ramstage.c index 76bbbaeca8..e70ba50498 100644 --- a/src/mainboard/starlabs/starbook/variants/adl_n/ramstage.c +++ b/src/mainboard/starlabs/starbook/variants/adl_n/ramstage.c @@ -1,13 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include "pin_mux.h" void mainboard_silicon_init_params(FSP_S_CONFIG *supd) { - /* - * FSP defaults to pins that are used for LPC; given that - * coreboot only supports eSPI, set these pins accordingly. - */ - supd->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 - supd->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 + configure_pin_mux(supd); } diff --git a/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c b/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c index e602932bfe..423716531a 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c +++ b/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c @@ -1,14 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include +#include "pin_mux.h" void mainboard_silicon_init_params(FSP_S_CONFIG *supd) { + configure_pin_mux(supd); supd->TcNotifyIgd = 2; // Auto - /* eSPI GPIOs */ - supd->SerialIoSpiCsPinMux[0] = 0x14a48a; - supd->SerialIoSpiClkPinMux[0] = 0x14a48b; - supd->SerialIoSpiMisoPinMux[0] = 0x14a48c; - supd->SerialIoSpiMosiPinMux[0] = 0x14a48d; } diff --git a/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c b/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c index f62c0698f0..e30afaa5ca 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c +++ b/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c @@ -2,15 +2,11 @@ #include #include +#include "pin_mux.h" void mainboard_silicon_init_params(FSP_S_CONFIG *supd) { - /* - * FSP defaults to pins that are used for LPC; given that - * coreboot only supports eSPI, set these pins accordingly. - */ - supd->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 - supd->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 + configure_pin_mux(supd); if (get_uint_option("thunderbolt", 1) == 0) supd->UsbTcPortEn = 0; diff --git a/src/mainboard/starlabs/starbook/variants/tgl/Makefile.mk b/src/mainboard/starlabs/starbook/variants/tgl/Makefile.mk index 2a505c35c7..9abc069b38 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/Makefile.mk +++ b/src/mainboard/starlabs/starbook/variants/tgl/Makefile.mk @@ -7,3 +7,4 @@ romstage-y += romstage.c ramstage-y += devtree.c ramstage-y += gpio.c ramstage-y += hda_verb.c +ramstage-y += ramstage.c diff --git a/src/mainboard/starlabs/starbook/variants/tgl/ramstage.c b/src/mainboard/starlabs/starbook/variants/tgl/ramstage.c new file mode 100644 index 0000000000..e70ba50498 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/tgl/ramstage.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "pin_mux.h" + +void mainboard_silicon_init_params(FSP_S_CONFIG *supd) +{ + configure_pin_mux(supd); +} diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c b/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c index f62c0698f0..e30afaa5ca 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c +++ b/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c @@ -2,15 +2,11 @@ #include #include +#include "pin_mux.h" void mainboard_silicon_init_params(FSP_S_CONFIG *supd) { - /* - * FSP defaults to pins that are used for LPC; given that - * coreboot only supports eSPI, set these pins accordingly. - */ - supd->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 - supd->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 + configure_pin_mux(supd); if (get_uint_option("thunderbolt", 1) == 0) supd->UsbTcPortEn = 0; diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c index 140101fb14..211384c1ef 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c @@ -3,17 +3,11 @@ #include #include #include +#include "pin_mux.h" void mainboard_silicon_init_params(FSP_S_CONFIG *supd) { - /* - * FSP defaults to pins that are used for LPC; given that - * coreboot only supports eSPI, set these pins accordingly. - */ - supd->CnviRfResetPinMux = 0x194ce404; // GPP_F4 - supd->CnviClkreqPinMux = 0x294ce605; // GPP_F5 - supd->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 - supd->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 + configure_pin_mux(supd); } const char *mainboard_vbt_filename(void)